src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 import operator
  33
  34
  35 # helper function for reducing a list of signals down to a parallel
  36 # ORed single signal.
  37 def ortreereduce(tree, attr="data_o"):
  38     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  39
  40
  41 class NonProductionCore(Elaboratable):
  42     def __init__(self):
  43         self.fus = AllFunctionUnits()
  44         self.regs = RegFiles()
  45         self.pdecode = pdecode = create_pdecode()
  46         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  47         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  48         self.issue_i = Signal(reset_less=True)
  49         self.busy_o = Signal(reset_less=True)
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         m.submodules.pdecode2 = dec2 = self.pdecode2
  55         m.submodules.fus = self.fus
  56         self.regs.elaborate_into(m, platform)
  57         regs = self.regs
  58         fus = self.fus.fus
  59
  60         fu_bitdict = self.connect_instruction(m)
  61         self.connect_rdports(m, fu_bitdict)
  62         self.connect_wrports(m, fu_bitdict)
  63
  64         return m
  65
  66     def connect_instruction(self, m):
  67         comb, sync = m.d.comb, m.d.sync
  68         fus = self.fus.fus
  69         dec2 = self.pdecode2
  70
  71         # enable-signals for each FU, get one bit for each FU (by name)
  72         fu_enable = Signal(len(fus), reset_less=True)
  73         fu_bitdict = {}
  74         for i, funame in enumerate(fus.keys()):
  75             fu_bitdict[funame] = fu_enable[i]
  76
  77         # connect up instructions.  only one is enabled at any given time
  78         for funame, fu in fus.items():
  79             fnunit = fu.fnunit.value
  80             enable = Signal(name="en_%s" % funame, reset_less=True)
  81             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  82             with m.If(enable):
  83                 comb += fu.oper_i.eq_from_execute1(dec2.e)
  84                 comb += fu.issue_i.eq(self.issue_i)
  85                 comb += self.busy_o.eq(fu.busy_o)
  86                 rdmask = dec2.rdflags(fu)
  87                 comb += fu.rdmaskn.eq(~rdmask)
  88             comb += fu_bitdict[funame].eq(enable)
  89
  90         return fu_bitdict
  91
  92     def connect_rdports(self, m, fu_bitdict):
  93         """connect read ports
  94
  95         orders the read regspecs into a dict-of-dicts, by regfile, by
  96         regport name, then connects all FUs that want that regport by
  97         way of a PriorityPicker.
  98         """
  99         comb, sync = m.d.comb, m.d.sync
 100         fus = self.fus.fus
 101         regs = self.regs
 102
 103         # dictionary of lists of regfile read ports
 104         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 105
 106         # okaay, now we need a PriorityPicker per regfile per regfile port
 107         # loootta pickers... peter piper picked a pack of pickled peppers...
 108         rdpickers = {}
 109         for regfile, spec in byregfiles_rd.items():
 110             fuspecs = byregfiles_rdspec[regfile]
 111             rdpickers[regfile] = {}
 112
 113             # for each named regfile port, connect up all FUs to that port
 114             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 115                 # get the regfile specs for this regfile port
 116                 (rf, read, write, wid, fuspec) = fspec
 117                 name = "rdflag_%s_%s" % (regfile, regname)
 118                 rdflag = Signal(name=name, reset_less=True)
 119                 comb += rdflag.eq(rf)
 120
 121                 # "munge" the regfile port index, due to full-port access
 122                 if regfile in ['XER', 'CA']:
 123                     if regname.startswith('full'):
 124                         rpidx = 0 # by convention, first port
 125                     else:
 126                         rpidx += 1 # start indexing port 0 from 1
 127
 128                 # select the required read port.  these are pre-defined sizes
 129                 print (regfile, regs.rf.keys())
 130                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 131
 132                 # create a priority picker to manage this port
 133                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 134                 setattr(m.submodules, "rdpick_%s_%d" % (regfile, rpidx), rdpick)
 135
 136                 # connect the regspec "reg select" number to this port
 137                 with m.If(rdpick.en_o):
 138                     comb += rport.ren.eq(read)
 139
 140                 # connect up the FU req/go signals, and the reg-read to the FU
 141                 # and create a Read Broadcast Bus
 142                 for pi, (funame, fu, idx) in enumerate(fuspec):
 143                     src = fu.src_i[idx]
 144
 145                     # connect request-read to picker input, and output to go-rd
 146                     fu_active = fu_bitdict[funame]
 147                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 148                     comb += rdpick.i[pi].eq(pick)
 149                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 150
 151                     # connect regfile port to input, creating a Broadcast Bus
 152                     print ("reg connect widths",
 153                            regfile, regname, pi, funame,
 154                            src.shape(), rport.data_o.shape())
 155                     comb += src.eq(rport.data_o) # all FUs connect to same port
 156
 157     def connect_wrports(self, m, fu_bitdict):
 158         """connect write ports
 159
 160         orders the write regspecs into a dict-of-dicts, by regfile,
 161         by regport name, then connects all FUs that want that regport
 162         by way of a PriorityPicker.
 163
 164         note that the write-port wen, write-port data, and go_wr_i all need to
 165         be on the exact same clock cycle.  as there is a combinatorial loop bug
 166         at the moment, these all use sync.
 167         """
 168         comb, sync = m.d.comb, m.d.sync
 169         fus = self.fus.fus
 170         regs = self.regs
 171         # dictionary of lists of regfile write ports
 172         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 173
 174         # same for write ports.
 175         # BLECH!  complex code-duplication! BLECH!
 176         wrpickers = {}
 177         for regfile, spec in byregfiles_wr.items():
 178             fuspecs = byregfiles_wrspec[regfile]
 179             wrpickers[regfile] = {}
 180             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 181                 # get the regfile specs for this regfile port
 182                 (rf, read, write, wid, fuspec) = fspec
 183
 184                 # "munge" the regfile port index, due to full-port access
 185                 if regfile in ['XER', 'CA']:
 186                     if regname.startswith('full'):
 187                         rpidx = 0 # by convention, first port
 188                     else:
 189                         rpidx += 1 # start indexing port 0 from 1
 190
 191                 # select the required write port.  these are pre-defined sizes
 192                 print (regfile, regs.rf.keys())
 193                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 194
 195                 # create a priority picker to manage this port
 196                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 197                 setattr(m.submodules, "wrpick_%s_%d" % (regfile, rpidx), wrpick)
 198
 199                 # connect the regspec write "reg select" number to this port
 200                 # only if one FU actually requests (and is granted) the port
 201                 # will the write-enable be activated
 202                 with m.If(wrpick.en_o):
 203                     sync += wport.wen.eq(write)
 204                 with m.Else():
 205                     sync += wport.wen.eq(0)
 206
 207                 # connect up the FU req/go signals and the reg-read to the FU
 208                 # these are arbitrated by Data.ok signals
 209                 wsigs = []
 210                 for pi, (funame, fu, idx) in enumerate(fuspec):
 211                     # write-request comes from dest.ok
 212                     dest = fu.get_out(idx)
 213                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 214                     wrflag = Signal(name=name, reset_less=True)
 215                     comb += wrflag.eq(dest.ok)
 216
 217                     # connect request-read to picker input, and output to go-wr
 218                     fu_active = fu_bitdict[funame]
 219                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 220                     comb += wrpick.i[pi].eq(pick)
 221                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 222                     # connect regfile port to input
 223                     print ("reg connect widths",
 224                            regfile, regname, pi, funame,
 225                            dest.shape(), wport.data_i.shape())
 226                     wsigs.append(dest)
 227
 228                 # here is where we create the Write Broadcast Bus. simple, eh?
 229                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 230
 231     def get_byregfiles(self, readmode):
 232
 233         mode = "read" if readmode else "write"
 234         dec2 = self.pdecode2
 235         regs = self.regs
 236         fus = self.fus.fus
 237
 238         # dictionary of lists of regfile ports
 239         byregfiles = {}
 240         byregfiles_spec = {}
 241         for (funame, fu) in fus.items():
 242             print ("%s ports for %s" % (mode, funame))
 243             for idx in range(fu.n_src if readmode else fu.n_dst):
 244                 if readmode:
 245                     (regfile, regname, wid) = fu.get_in_spec(idx)
 246                 else:
 247                     (regfile, regname, wid) = fu.get_out_spec(idx)
 248                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 249                 rdflag, read, write = dec2.regspecmap(regfile, regname)
 250                 if regfile not in byregfiles:
 251                     byregfiles[regfile] = {}
 252                     byregfiles_spec[regfile] = {}
 253                 if regname not in byregfiles_spec[regfile]:
 254                     byregfiles_spec[regfile][regname] = \
 255                                 [rdflag, read, write, wid, []]
 256                 # here we start to create "lanes"
 257                 if idx not in byregfiles[regfile]:
 258                     byregfiles[regfile][idx] = []
 259                 fuspec = (funame, fu, idx)
 260                 byregfiles[regfile][idx].append(fuspec)
 261                 byregfiles_spec[regfile][regname][4].append(fuspec)
 262
 263         # ok just print that out, for convenience
 264         for regfile, spec in byregfiles.items():
 265             print ("regfile %s ports:" % mode, regfile)
 266             fuspecs = byregfiles_spec[regfile]
 267             for regname, fspec in fuspecs.items():
 268                 [rdflag, read, write, wid, fuspec] = fspec
 269                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 270                 print ("  %s" % regname, wid, read, write, rdflag)
 271                 for (funame, fu, idx) in fuspec:
 272                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 273                     print ("    ", funame, fu, idx, fusig)
 274                     print ()
 275
 276         return byregfiles, byregfiles_spec
 277
 278     def __iter__(self):
 279         yield from self.fus.ports()
 280         yield from self.pdecode2.ports()
 281         # TODO: regs
 282
 283     def ports(self):
 284         return list(self)
 285
 286
 287 if __name__ == '__main__':
 288     dut = NonProductionCore()
 289     vl = rtlil.convert(dut, ports=dut.ports())
 290     with open("non_production_core.il", "w") as f:
 291         f.write(vl)