1 """simple core input data
5 from nmigen
import Signal
7 from openpower
.sv
.svp64
import SVP64Rec
9 from openpower
.decoder
.decode2execute1
import Decode2ToExecute1Type
10 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
11 from soc
.config
.state
import CoreState
15 """FetchOutput: the output from the fetch unit: one single instruction
17 * state. this contains PC, MSR, and SVSTATE. this is crucial information.
18 (TODO: bigendian_i should really be read from the relevant MSR bit)
20 * the raw instruction. no decoding has been done - at all.
22 (TODO: provide a *pair* of raw instructions so that packet
23 inspection can be done, and SVP64 decoding and future 64-bit
24 prefix analysis carried out. however right now that is *not*
27 def __init__(self
): #, svp64_en):
28 #self.svp64_en = svp64_en
30 # state and raw instruction (and SVP64 ReMap fields)
31 self
.state
= CoreState("core_fetched")
32 self
.raw_insn_i
= Signal(32) # one raw instruction
33 self
.bigendian_i
= Signal() # bigendian - TODO, set by MSR.BE
36 self
.state
.eq(i
.state
)
37 self
.raw_insn_i
.eq(i
.raw_insn_i
)
38 self
.bigendian_i
.eq(i
.bigendian_i
)
42 """CoreInput: this is the input specification for Signals coming into core.
44 * state. this contains PC, MSR, and SVSTATE. this is crucial information.
45 (TODO: bigendian_i should really be read from the relevant MSR bit)
47 * the previously-decoded instruction goes into the Decode2Execute1Type
48 data structure. no need for Core to re-decode that. however note
49 that *satellite* decoders *are* part of Core.
51 * the raw instruction. this is used by satellite decoders internal to
52 Core, to provide Function-Unit-specific information. really, they
53 should be part of the actual ALU itself (in order to reduce wires),
56 * other stuff is related to SVP64. the 24-bit SV REMAP field containing
59 def __init__(self
, pspec
, svp64_en
, regreduce_en
):
61 self
.svp64_en
= svp64_en
62 self
.e
= Decode2ToExecute1Type("core", opkls
=IssuerDecode2ToOperand
,
63 regreduce_en
=regreduce_en
)
65 # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
66 self
.sv_a_nz
= Signal()
68 # state and raw instruction (and SVP64 ReMap fields)
69 self
.state
= CoreState("core")
70 self
.raw_insn_i
= Signal(32) # raw instruction
71 self
.bigendian_i
= Signal() # bigendian - TODO, set by MSR.BE
73 self
.sv_rm
= SVP64Rec(name
="core_svp64_rm") # SVP64 RM field
74 self
.is_svp64_mode
= Signal() # set if SVP64 mode is enabled
75 self
.use_svp64_ldst_dec
= Signal() # use alternative LDST decoder
76 self
.sv_pred_sm
= Signal() # TODO: SIMD width
77 self
.sv_pred_dm
= Signal() # TODO: SIMD width
81 self
.sv_a_nz
.eq(i
.sv_a_nz
)
82 self
.state
.eq(i
.state
)
83 self
.raw_insn_i
.eq(i
.raw_insn_i
)
84 self
.bigendian_i
.eq(i
.bigendian_i
)
87 self
.sv_rm
.eq(i
.sv_rm
)
88 self
.is_svp64_mode
.eq(i
.is_svp64_mode
)
89 self
.use_svp64_ldst_dec
.eq(i
.use_svp64_ldst_dec
)
90 self
.sv_pred_sm
.eq(i
.sv_pred_sm
)
91 self
.sv_pred_dm
.eq(i
.sv_pred_dm
)
96 # start/stop and terminated signalling
97 self
.core_terminate_o
= Signal() # indicates stopped
98 self
.busy_o
= Signal(name
="corebusy_o") # at least one ALU busy
99 self
.exc_happened
= Signal() # exception happened
102 self
.core_terminate_o
.eq(i
.core_terminate_o
)
103 self
.busy_o
.eq(i
.busy_o
)
104 self
.exc_happened
.eq(i
.exc_happened
)