01c45ef8a0d60d22e288cc05ae081d6930be8736
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from soc.decoder.power_decoder import create_pdecode
25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
27 from soc.decoder.decode2execute1 import Data
28 from soc.experiment.testmem import TestMemory # test only for instructions
29 from soc.regfile.regfiles import StateRegs, FastRegs
30 from soc.simple.core import NonProductionCore
31 from soc.config.test.test_loadstore import TestMemPspec
32 from soc.config.ifetch import ConfigFetchUnit
33 from soc.decoder.power_enums import MicrOp
34 from soc.debug.dmi import CoreDebug, DMIInterface
35 from soc.debug.jtag import JTAG
36 from soc.config.pinouts import get_pinspecs
37 from soc.config.state import CoreState
38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
39 from soc.bus.simple_gpio import SimpleGPIO
40 from soc.clock.select import ClockSelect
41 from soc.clock.dummypll import DummyPLL
42
43
44 from nmutil.util import rising_edge
45
46
47 class TestIssuerInternal(Elaboratable):
48 """TestIssuer - reads instructions from TestMemory and issues them
49
50 efficiency and speed is not the main goal here: functional correctness is.
51 """
52 def __init__(self, pspec):
53
54 # JTAG interface. add this right at the start because if it's
55 # added it *modifies* the pspec, by adding enable/disable signals
56 # for parts of the rest of the core
57 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
58 if self.jtag_en:
59 subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
60 'pwm', 'sd0', 'sdr'}
61 self.jtag = JTAG(get_pinspecs(subset=subset))
62 # add signals to pspec to enable/disable icache and dcache
63 # (or data and intstruction wishbone if icache/dcache not included)
64 # https://bugs.libre-soc.org/show_bug.cgi?id=520
65 # TODO: do we actually care if these are not domain-synchronised?
66 # honestly probably not.
67 pspec.wb_icache_en = self.jtag.wb_icache_en
68 pspec.wb_dcache_en = self.jtag.wb_dcache_en
69
70 # add interrupt controller?
71 self.xics = hasattr(pspec, "xics") and pspec.xics == True
72 if self.xics:
73 self.xics_icp = XICS_ICP()
74 self.xics_ics = XICS_ICS()
75 self.int_level_i = self.xics_ics.int_level_i
76
77 # add GPIO peripheral?
78 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
79 if self.gpio:
80 self.simple_gpio = SimpleGPIO()
81 self.gpio_o = self.simple_gpio.gpio_o
82
83 # main instruction core25
84 self.core = core = NonProductionCore(pspec)
85
86 # instruction decoder. goes into Trap Record
87 pdecode = create_pdecode()
88 self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
89 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
90 opkls=IssuerDecode2ToOperand)
91 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
92
93 # Test Instruction memory
94 self.imem = ConfigFetchUnit(pspec).fu
95 # one-row cache of instruction read
96 self.iline = Signal(64) # one instruction line
97 self.iprev_adr = Signal(64) # previous address: if different, do read
98
99 # DMI interface
100 self.dbg = CoreDebug()
101
102 # instruction go/monitor
103 self.pc_o = Signal(64, reset_less=True)
104 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
105 self.core_bigendian_i = Signal()
106 self.busy_o = Signal(reset_less=True)
107 self.memerr_o = Signal(reset_less=True)
108
109 # FAST regfile read /write ports for PC, MSR, DEC/TB
110 staterf = self.core.regs.rf['state']
111 self.state_r_pc = staterf.r_ports['cia'] # PC rd
112 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
113 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
114
115 # DMI interface access
116 intrf = self.core.regs.rf['int']
117 crrf = self.core.regs.rf['cr']
118 xerrf = self.core.regs.rf['xer']
119 self.int_r = intrf.r_ports['dmi'] # INT read
120 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
121 self.xer_r = xerrf.r_ports['full_xer'] # XER read
122
123 # hack method of keeping an eye on whether branch/trap set the PC
124 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
125 self.state_nia.wen.name = 'state_nia_wen'
126
127 def elaborate(self, platform):
128 m = Module()
129 comb, sync = m.d.comb, m.d.sync
130
131 m.submodules.core = core = DomainRenamer("coresync")(self.core)
132 m.submodules.imem = imem = self.imem
133 m.submodules.dbg = dbg = self.dbg
134 if self.jtag_en:
135 m.submodules.jtag = jtag = self.jtag
136 # TODO: UART2GDB mux, here, from external pin
137 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
138 sync += dbg.dmi.connect_to(jtag.dmi)
139
140 cur_state = self.cur_state
141
142 # XICS interrupt handler
143 if self.xics:
144 m.submodules.xics_icp = icp = self.xics_icp
145 m.submodules.xics_ics = ics = self.xics_ics
146 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
147 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
148
149 # GPIO test peripheral
150 if self.gpio:
151 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
152
153 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
154 # XXX causes litex ECP5 test to get wrong idea about input and output
155 # (but works with verilator sim *sigh*)
156 #if self.gpio and self.xics:
157 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
158
159 # instruction decoder
160 pdecode = create_pdecode()
161 m.submodules.dec2 = pdecode2 = self.pdecode2
162
163 # convenience
164 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
165 intrf = self.core.regs.rf['int']
166
167 # clock delay power-on reset
168 cd_por = ClockDomain(reset_less=True)
169 cd_sync = ClockDomain()
170 core_sync = ClockDomain("coresync")
171 m.domains += cd_por, cd_sync, core_sync
172
173 ti_rst = Signal(reset_less=True)
174 delay = Signal(range(4), reset=3)
175 with m.If(delay != 0):
176 m.d.por += delay.eq(delay - 1)
177 comb += cd_por.clk.eq(ClockSignal())
178
179 # power-on reset delay
180 core_rst = ResetSignal("coresync")
181 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
182 comb += core_rst.eq(ti_rst)
183
184 # busy/halted signals from core
185 comb += self.busy_o.eq(core.busy_o)
186 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
187
188 # temporary hack: says "go" immediately for both address gen and ST
189 l0 = core.l0
190 ldst = core.fus.fus['ldst0']
191 st_go_edge = rising_edge(m, ldst.st.rel_o)
192 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
193 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
194
195 # PC and instruction from I-Memory
196 pc_changed = Signal() # note write to PC
197 comb += self.pc_o.eq(cur_state.pc)
198 ilatch = Signal(32)
199
200 # next instruction (+4 on current)
201 nia = Signal(64, reset_less=True)
202 comb += nia.eq(cur_state.pc + 4)
203
204 # read the PC
205 pc = Signal(64, reset_less=True)
206 pc_ok_delay = Signal()
207 sync += pc_ok_delay.eq(~self.pc_i.ok)
208 with m.If(self.pc_i.ok):
209 # incoming override (start from pc_i)
210 comb += pc.eq(self.pc_i.data)
211 with m.Else():
212 # otherwise read StateRegs regfile for PC...
213 comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
214 # ... but on a 1-clock delay
215 with m.If(pc_ok_delay):
216 comb += pc.eq(self.state_r_pc.data_o)
217
218 # don't write pc every cycle
219 comb += self.state_w_pc.wen.eq(0)
220 comb += self.state_w_pc.data_i.eq(0)
221
222 # don't read msr every cycle
223 comb += self.state_r_msr.ren.eq(0)
224 msr_read = Signal(reset=1)
225
226 # connect up debug signals
227 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
228 comb += dbg.terminate_i.eq(core.core_terminate_o)
229 comb += dbg.state.pc.eq(pc)
230 #comb += dbg.state.pc.eq(cur_state.pc)
231 comb += dbg.state.msr.eq(cur_state.msr)
232
233 # temporaries
234 core_busy_o = core.busy_o # core is busy
235 core_ivalid_i = core.ivalid_i # instruction is valid
236 core_issue_i = core.issue_i # instruction is issued
237 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
238
239 insn_type = core.e.do.insn_type
240
241 # handshake signals between fetch and decode/execute
242 # fetch FSM can run as soon as the PC is valid
243 fetch_pc_valid_i = Signal()
244 fetch_pc_ready_o = Signal()
245 # when done, deliver the instruction to the next FSM
246 fetch_insn_o = Signal(32, reset_less=True)
247 fetch_insn_valid_o = Signal()
248 fetch_insn_ready_i = Signal()
249
250 # actually use a nmigen FSM for the first time (w00t)
251 # this FSM is perhaps unusual in that it detects conditions
252 # then "holds" information, combinatorially, for the core
253 # (as opposed to using sync - which would be on a clock's delay)
254 # this includes the actual opcode, valid flags and so on.
255 with m.FSM(name='fetch_fsm'):
256
257 # waiting (zzz)
258 with m.State("IDLE"):
259 with m.If(~dbg.core_stop_o & ~core_rst):
260 comb += fetch_pc_ready_o.eq(1)
261 with m.If(fetch_pc_valid_i):
262 # instruction allowed to go: start by reading the PC
263 # capture the PC and also drop it into Insn Memory
264 # we have joined a pair of combinatorial memory
265 # lookups together. this is Generally Bad.
266 comb += self.imem.a_pc_i.eq(pc)
267 comb += self.imem.a_valid_i.eq(1)
268 comb += self.imem.f_valid_i.eq(1)
269 sync += cur_state.pc.eq(pc)
270
271 # initiate read of MSR. arrives one clock later
272 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
273 sync += msr_read.eq(0)
274
275 m.next = "INSN_READ" # move to "wait for bus" phase
276 with m.Else():
277 comb += core.core_stopped_i.eq(1)
278 comb += dbg.core_stopped_i.eq(1)
279
280 # dummy pause to find out why simulation is not keeping up
281 with m.State("INSN_READ"):
282 # one cycle later, msr read arrives. valid only once.
283 with m.If(~msr_read):
284 sync += msr_read.eq(1) # yeah don't read it again
285 sync += cur_state.msr.eq(self.state_r_msr.data_o)
286 with m.If(self.imem.f_busy_o): # zzz...
287 # busy: stay in wait-read
288 comb += self.imem.a_valid_i.eq(1)
289 comb += self.imem.f_valid_i.eq(1)
290 with m.Else():
291 # not busy: instruction fetched
292 f_instr_o = self.imem.f_instr_o
293 if f_instr_o.width == 32:
294 insn = f_instr_o
295 else:
296 insn = f_instr_o.word_select(cur_state.pc[2], 32)
297 # capture and hold the instruction from memory
298 sync += fetch_insn_o.eq(insn)
299 m.next = "INSN_READY"
300
301 with m.State("INSN_READY"):
302 # hand over the instruction, to be decoded
303 comb += fetch_insn_valid_o.eq(1)
304 with m.If(fetch_insn_ready_i):
305 m.next = "IDLE"
306
307 # decode / issue / execute FSM
308 with m.FSM():
309
310 # go fetch the instruction at the current PC
311 # at this point, there is no instruction running, that
312 # could inadvertently update the PC.
313 with m.State("INSN_FETCH"):
314 comb += fetch_pc_valid_i.eq(1)
315 with m.If(fetch_pc_ready_o):
316 m.next = "INSN_WAIT"
317
318 # decode the instruction when it arrives
319 with m.State("INSN_WAIT"):
320 comb += fetch_insn_ready_i.eq(1)
321 with m.If(fetch_insn_valid_o):
322 # decode the instruction
323 # TODO, before issuing new instruction first
324 # check if it's SVP64. (svp64.is_svp64_mode set)
325 # if yes, record the svp64_rm, put that into
326 # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
327 comb += dec_opcode_i.eq(fetch_insn_o) # actual opcode
328 sync += core.e.eq(pdecode2.e)
329 sync += core.state.eq(cur_state)
330 sync += core.raw_insn_i.eq(dec_opcode_i)
331 sync += core.bigendian_i.eq(self.core_bigendian_i)
332 sync += ilatch.eq(insn) # latch current insn
333 # also drop PC and MSR into decode "state"
334 m.next = "INSN_START" # move to "start"
335
336 # waiting for instruction bus (stays there until not busy)
337 with m.State("INSN_START"):
338 comb += core_ivalid_i.eq(1) # instruction is valid
339 comb += core_issue_i.eq(1) # and issued
340 sync += pc_changed.eq(0)
341
342 m.next = "INSN_ACTIVE" # move to "wait completion"
343
344 # instruction started: must wait till it finishes
345 with m.State("INSN_ACTIVE"):
346 with m.If(insn_type != MicrOp.OP_NOP):
347 comb += core_ivalid_i.eq(1) # instruction is valid
348 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
349 sync += pc_changed.eq(1)
350 with m.If(~core_busy_o): # instruction done!
351 # ok here we are not reading the branch unit. TODO
352 # this just blithely overwrites whatever pipeline
353 # updated the PC
354 with m.If(~pc_changed):
355 comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
356 comb += self.state_w_pc.data_i.eq(nia)
357 sync += core.e.eq(0)
358 sync += core.raw_insn_i.eq(0)
359 sync += core.bigendian_i.eq(0)
360 m.next = "INSN_FETCH" # back to fetch
361
362 # this bit doesn't have to be in the FSM: connect up to read
363 # regfiles on demand from DMI
364 with m.If(d_reg.req): # request for regfile access being made
365 # TODO: error-check this
366 # XXX should this be combinatorial? sync better?
367 if intrf.unary:
368 comb += self.int_r.ren.eq(1<<d_reg.addr)
369 else:
370 comb += self.int_r.addr.eq(d_reg.addr)
371 comb += self.int_r.ren.eq(1)
372 d_reg_delay = Signal()
373 sync += d_reg_delay.eq(d_reg.req)
374 with m.If(d_reg_delay):
375 # data arrives one clock later
376 comb += d_reg.data.eq(self.int_r.data_o)
377 comb += d_reg.ack.eq(1)
378
379 # sigh same thing for CR debug
380 with m.If(d_cr.req): # request for regfile access being made
381 comb += self.cr_r.ren.eq(0b11111111) # enable all
382 d_cr_delay = Signal()
383 sync += d_cr_delay.eq(d_cr.req)
384 with m.If(d_cr_delay):
385 # data arrives one clock later
386 comb += d_cr.data.eq(self.cr_r.data_o)
387 comb += d_cr.ack.eq(1)
388
389 # aaand XER...
390 with m.If(d_xer.req): # request for regfile access being made
391 comb += self.xer_r.ren.eq(0b111111) # enable all
392 d_xer_delay = Signal()
393 sync += d_xer_delay.eq(d_xer.req)
394 with m.If(d_xer_delay):
395 # data arrives one clock later
396 comb += d_xer.data.eq(self.xer_r.data_o)
397 comb += d_xer.ack.eq(1)
398
399 # DEC and TB inc/dec FSM
400 self.tb_dec_fsm(m, cur_state.dec)
401
402 return m
403
404 def tb_dec_fsm(self, m, spr_dec):
405 """tb_dec_fsm
406
407 this is a FSM for updating either dec or tb. it runs alternately
408 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
409 value to DEC, however the regfile has "passthrough" on it so this
410 *should* be ok.
411
412 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
413 """
414
415 comb, sync = m.d.comb, m.d.sync
416 fast_rf = self.core.regs.rf['fast']
417 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
418 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
419
420 with m.FSM() as fsm:
421
422 # initiates read of current DEC
423 with m.State("DEC_READ"):
424 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
425 comb += fast_r_dectb.ren.eq(1)
426 m.next = "DEC_WRITE"
427
428 # waits for DEC read to arrive (1 cycle), updates with new value
429 with m.State("DEC_WRITE"):
430 new_dec = Signal(64)
431 # TODO: MSR.LPCR 32-bit decrement mode
432 comb += new_dec.eq(fast_r_dectb.data_o - 1)
433 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
434 comb += fast_w_dectb.wen.eq(1)
435 comb += fast_w_dectb.data_i.eq(new_dec)
436 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
437 m.next = "TB_READ"
438
439 # initiates read of current TB
440 with m.State("TB_READ"):
441 comb += fast_r_dectb.addr.eq(FastRegs.TB)
442 comb += fast_r_dectb.ren.eq(1)
443 m.next = "TB_WRITE"
444
445 # waits for read TB to arrive, initiates write of current TB
446 with m.State("TB_WRITE"):
447 new_tb = Signal(64)
448 comb += new_tb.eq(fast_r_dectb.data_o + 1)
449 comb += fast_w_dectb.addr.eq(FastRegs.TB)
450 comb += fast_w_dectb.wen.eq(1)
451 comb += fast_w_dectb.data_i.eq(new_tb)
452 m.next = "DEC_READ"
453
454 return m
455
456 def __iter__(self):
457 yield from self.pc_i.ports()
458 yield self.pc_o
459 yield self.memerr_o
460 yield from self.core.ports()
461 yield from self.imem.ports()
462 yield self.core_bigendian_i
463 yield self.busy_o
464
465 def ports(self):
466 return list(self)
467
468 def external_ports(self):
469 ports = self.pc_i.ports()
470 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
471 ]
472
473 if self.jtag_en:
474 ports += list(self.jtag.external_ports())
475 else:
476 # don't add DMI if JTAG is enabled
477 ports += list(self.dbg.dmi.ports())
478
479 ports += list(self.imem.ibus.fields.values())
480 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
481
482 if self.xics:
483 ports += list(self.xics_icp.bus.fields.values())
484 ports += list(self.xics_ics.bus.fields.values())
485 ports.append(self.int_level_i)
486
487 if self.gpio:
488 ports += list(self.simple_gpio.bus.fields.values())
489 ports.append(self.gpio_o)
490
491 return ports
492
493 def ports(self):
494 return list(self)
495
496
497 class TestIssuer(Elaboratable):
498 def __init__(self, pspec):
499 self.ti = TestIssuerInternal(pspec)
500
501 self.pll = DummyPLL()
502
503 # PLL direct clock or not
504 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
505 if self.pll_en:
506 self.pll_18_o = Signal(reset_less=True)
507
508 def elaborate(self, platform):
509 m = Module()
510 comb = m.d.comb
511
512 # TestIssuer runs at direct clock
513 m.submodules.ti = ti = self.ti
514 cd_int = ClockDomain("coresync")
515
516 if self.pll_en:
517 # ClockSelect runs at PLL output internal clock rate
518 m.submodules.pll = pll = self.pll
519
520 # add clock domains from PLL
521 cd_pll = ClockDomain("pllclk")
522 m.domains += cd_pll
523
524 # PLL clock established. has the side-effect of running clklsel
525 # at the PLL's speed (see DomainRenamer("pllclk") above)
526 pllclk = ClockSignal("pllclk")
527 comb += pllclk.eq(pll.clk_pll_o)
528
529 # wire up external 24mhz to PLL
530 comb += pll.clk_24_i.eq(ClockSignal())
531
532 # output 18 mhz PLL test signal
533 comb += self.pll_18_o.eq(pll.pll_18_o)
534
535 # now wire up ResetSignals. don't mind them being in this domain
536 pll_rst = ResetSignal("pllclk")
537 comb += pll_rst.eq(ResetSignal())
538
539 # internal clock is set to selector clock-out. has the side-effect of
540 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
541 intclk = ClockSignal("coresync")
542 if self.pll_en:
543 comb += intclk.eq(pll.clk_pll_o)
544 else:
545 comb += intclk.eq(ClockSignal())
546
547 return m
548
549 def ports(self):
550 return list(self.ti.ports()) + list(self.pll.ports()) + \
551 [ClockSignal(), ResetSignal()]
552
553 def external_ports(self):
554 ports = self.ti.external_ports()
555 ports.append(ClockSignal())
556 ports.append(ResetSignal())
557 if self.pll_en:
558 ports.append(self.pll.clk_sel_i)
559 ports.append(self.pll_18_o)
560 ports.append(self.pll.pll_lck_o)
561 return ports
562
563
564 if __name__ == '__main__':
565 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
566 'spr': 1,
567 'div': 1,
568 'mul': 1,
569 'shiftrot': 1
570 }
571 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
572 imem_ifacetype='bare_wb',
573 addr_wid=48,
574 mask_wid=8,
575 reg_wid=64,
576 units=units)
577 dut = TestIssuer(pspec)
578 vl = main(dut, ports=dut.ports(), name="test_issuer")
579
580 if len(sys.argv) == 1:
581 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
582 with open("test_issuer.il", "w") as f:
583 f.write(vl)