3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmigen
.lib
.coding
import PriorityEncoder
26 from openpower
.decoder
.power_decoder
import create_pdecode
27 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
28 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
29 from openpower
.decoder
.decode2execute1
import Data
30 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
32 from openpower
.state
import CoreState
33 from openpower
.consts
import (CR
, SVP64CROffs
)
34 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
35 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
36 from soc
.simple
.core
import NonProductionCore
37 from soc
.config
.test
.test_loadstore
import TestMemPspec
38 from soc
.config
.ifetch
import ConfigFetchUnit
39 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
40 from soc
.debug
.jtag
import JTAG
41 from soc
.config
.pinouts
import get_pinspecs
42 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
43 from soc
.bus
.simple_gpio
import SimpleGPIO
44 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
45 from soc
.clock
.select
import ClockSelect
46 from soc
.clock
.dummypll
import DummyPLL
47 from openpower
.sv
.svstate
import SVSTATERec
50 from nmutil
.util
import rising_edge
52 def get_insn(f_instr_o
, pc
):
53 if f_instr_o
.width
== 32:
56 # 64-bit: bit 2 of pc decides which word to select
57 return f_instr_o
.word_select(pc
[2], 32)
59 # gets state input or reads from state regfile
60 def state_get(m
, core_rst
, state_i
, name
, regfile
, regnum
):
64 res
= Signal(64, reset_less
=True, name
=name
)
65 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
67 sync
+= res_ok_delay
.eq(~state_i
.ok
)
68 with m
.If(state_i
.ok
):
69 # incoming override (start from pc_i)
70 comb
+= res
.eq(state_i
.data
)
72 # otherwise read StateRegs regfile for PC...
73 comb
+= regfile
.ren
.eq(1<<regnum
)
74 # ... but on a 1-clock delay
75 with m
.If(res_ok_delay
):
76 comb
+= res
.eq(regfile
.o_data
)
79 def get_predint(m
, mask
, name
):
80 """decode SVP64 predicate integer mask field to reg number and invert
81 this is identical to the equivalent function in ISACaller except that
82 it doesn't read the INT directly, it just decodes "what needs to be done"
83 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
85 * all1s is set to indicate that no mask is to be applied.
86 * regread indicates the GPR register number to be read
87 * invert is set to indicate that the register value is to be inverted
88 * unary indicates that the contents of the register is to be shifted 1<<r3
91 regread
= Signal(5, name
=name
+"regread")
92 invert
= Signal(name
=name
+"invert")
93 unary
= Signal(name
=name
+"unary")
94 all1s
= Signal(name
=name
+"all1s")
96 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
97 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
98 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
100 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
101 with m
.Case(SVP64PredInt
.R3
.value
):
102 comb
+= regread
.eq(3)
103 with m
.Case(SVP64PredInt
.R3_N
.value
):
104 comb
+= regread
.eq(3)
106 with m
.Case(SVP64PredInt
.R10
.value
):
107 comb
+= regread
.eq(10)
108 with m
.Case(SVP64PredInt
.R10_N
.value
):
109 comb
+= regread
.eq(10)
111 with m
.Case(SVP64PredInt
.R30
.value
):
112 comb
+= regread
.eq(30)
113 with m
.Case(SVP64PredInt
.R30_N
.value
):
114 comb
+= regread
.eq(30)
116 return regread
, invert
, unary
, all1s
118 def get_predcr(m
, mask
, name
):
119 """decode SVP64 predicate CR to reg number field and invert status
120 this is identical to _get_predcr in ISACaller
123 idx
= Signal(2, name
=name
+"idx")
124 invert
= Signal(name
=name
+"crinvert")
126 with m
.Case(SVP64PredCR
.LT
.value
):
127 comb
+= idx
.eq(CR
.LT
)
129 with m
.Case(SVP64PredCR
.GE
.value
):
130 comb
+= idx
.eq(CR
.LT
)
132 with m
.Case(SVP64PredCR
.GT
.value
):
133 comb
+= idx
.eq(CR
.GT
)
135 with m
.Case(SVP64PredCR
.LE
.value
):
136 comb
+= idx
.eq(CR
.GT
)
138 with m
.Case(SVP64PredCR
.EQ
.value
):
139 comb
+= idx
.eq(CR
.EQ
)
141 with m
.Case(SVP64PredCR
.NE
.value
):
142 comb
+= idx
.eq(CR
.EQ
)
144 with m
.Case(SVP64PredCR
.SO
.value
):
145 comb
+= idx
.eq(CR
.SO
)
147 with m
.Case(SVP64PredCR
.NS
.value
):
148 comb
+= idx
.eq(CR
.SO
)
153 class TestIssuerInternal(Elaboratable
):
154 """TestIssuer - reads instructions from TestMemory and issues them
156 efficiency and speed is not the main goal here: functional correctness
157 and code clarity is. optimisations (which almost 100% interfere with
158 easy understanding) come later.
160 def __init__(self
, pspec
):
162 # test is SVP64 is to be enabled
163 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
165 # and if regfiles are reduced
166 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
167 (pspec
.regreduce
== True))
169 # JTAG interface. add this right at the start because if it's
170 # added it *modifies* the pspec, by adding enable/disable signals
171 # for parts of the rest of the core
172 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
173 self
.dbg_domain
= "sync" # sigh "dbgsunc" too problematic
174 #self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
176 # XXX MUST keep this up-to-date with litex, and
177 # soc-cocotb-sim, and err.. all needs sorting out, argh
180 'eint', 'gpio', 'mspi0',
181 # 'mspi1', - disabled for now
182 # 'pwm', 'sd0', - disabled for now
184 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
185 domain
=self
.dbg_domain
)
186 # add signals to pspec to enable/disable icache and dcache
187 # (or data and intstruction wishbone if icache/dcache not included)
188 # https://bugs.libre-soc.org/show_bug.cgi?id=520
189 # TODO: do we actually care if these are not domain-synchronised?
190 # honestly probably not.
191 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
192 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
193 self
.wb_sram_en
= self
.jtag
.wb_sram_en
195 self
.wb_sram_en
= Const(1)
197 # add 4k sram blocks?
198 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
199 pspec
.sram4x4kblock
== True)
203 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
207 # add interrupt controller?
208 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
210 self
.xics_icp
= XICS_ICP()
211 self
.xics_ics
= XICS_ICS()
212 self
.int_level_i
= self
.xics_ics
.int_level_i
214 # add GPIO peripheral?
215 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
217 self
.simple_gpio
= SimpleGPIO()
218 self
.gpio_o
= self
.simple_gpio
.gpio_o
220 # main instruction core. suitable for prototyping / demo only
221 self
.core
= core
= NonProductionCore(pspec
)
222 self
.core_rst
= ResetSignal("coresync")
224 # instruction decoder. goes into Trap Record
225 #pdecode = create_pdecode()
226 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
227 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
228 opkls
=IssuerDecode2ToOperand
,
229 svp64_en
=self
.svp64_en
,
230 regreduce_en
=self
.regreduce_en
)
231 pdecode
= self
.pdecode2
.dec
234 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
236 # Test Instruction memory
237 self
.imem
= ConfigFetchUnit(pspec
).fu
240 self
.dbg
= CoreDebug()
242 # instruction go/monitor
243 self
.pc_o
= Signal(64, reset_less
=True)
244 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
245 self
.svstate_i
= Data(64, "svstate_i") # ditto
246 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
247 self
.busy_o
= Signal(reset_less
=True)
248 self
.memerr_o
= Signal(reset_less
=True)
250 # STATE regfile read /write ports for PC, MSR, SVSTATE
251 staterf
= self
.core
.regs
.rf
['state']
252 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
253 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
254 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
255 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
256 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
258 # DMI interface access
259 intrf
= self
.core
.regs
.rf
['int']
260 crrf
= self
.core
.regs
.rf
['cr']
261 xerrf
= self
.core
.regs
.rf
['xer']
262 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
263 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
264 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
268 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
269 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
271 # hack method of keeping an eye on whether branch/trap set the PC
272 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
273 self
.state_nia
.wen
.name
= 'state_nia_wen'
275 # pulse to synchronize the simulator at instruction end
276 self
.insn_done
= Signal()
279 # store copies of predicate masks
280 self
.srcmask
= Signal(64)
281 self
.dstmask
= Signal(64)
283 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
284 fetch_pc_o_ready
, fetch_pc_i_valid
,
285 fetch_insn_o_valid
, fetch_insn_i_ready
):
288 this FSM performs fetch of raw instruction data, partial-decodes
289 it 32-bit at a time to detect SVP64 prefixes, and will optionally
290 read a 2nd 32-bit quantity if that occurs.
294 pdecode2
= self
.pdecode2
295 cur_state
= self
.cur_state
296 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
298 msr_read
= Signal(reset
=1)
300 with m
.FSM(name
='fetch_fsm'):
303 with m
.State("IDLE"):
304 comb
+= fetch_pc_o_ready
.eq(1)
305 with m
.If(fetch_pc_i_valid
):
306 # instruction allowed to go: start by reading the PC
307 # capture the PC and also drop it into Insn Memory
308 # we have joined a pair of combinatorial memory
309 # lookups together. this is Generally Bad.
310 comb
+= self
.imem
.a_pc_i
.eq(pc
)
311 comb
+= self
.imem
.a_i_valid
.eq(1)
312 comb
+= self
.imem
.f_i_valid
.eq(1)
313 sync
+= cur_state
.pc
.eq(pc
)
314 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
316 # initiate read of MSR. arrives one clock later
317 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
318 sync
+= msr_read
.eq(0)
320 m
.next
= "INSN_READ" # move to "wait for bus" phase
322 # dummy pause to find out why simulation is not keeping up
323 with m
.State("INSN_READ"):
324 # one cycle later, msr/sv read arrives. valid only once.
325 with m
.If(~msr_read
):
326 sync
+= msr_read
.eq(1) # yeah don't read it again
327 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.o_data
)
328 with m
.If(self
.imem
.f_busy_o
): # zzz...
329 # busy: stay in wait-read
330 comb
+= self
.imem
.a_i_valid
.eq(1)
331 comb
+= self
.imem
.f_i_valid
.eq(1)
333 # not busy: instruction fetched
334 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
337 # decode the SVP64 prefix, if any
338 comb
+= svp64
.raw_opcode_in
.eq(insn
)
339 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
340 # pass the decoded prefix (if any) to PowerDecoder2
341 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
342 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
343 # remember whether this is a prefixed instruction, so
344 # the FSM can readily loop when VL==0
345 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
346 # calculate the address of the following instruction
347 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
348 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
349 with m
.If(~svp64
.is_svp64_mode
):
350 # with no prefix, store the instruction
351 # and hand it directly to the next FSM
352 sync
+= dec_opcode_i
.eq(insn
)
353 m
.next
= "INSN_READY"
355 # fetch the rest of the instruction from memory
356 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
357 comb
+= self
.imem
.a_i_valid
.eq(1)
358 comb
+= self
.imem
.f_i_valid
.eq(1)
359 m
.next
= "INSN_READ2"
361 # not SVP64 - 32-bit only
362 sync
+= nia
.eq(cur_state
.pc
+ 4)
363 sync
+= dec_opcode_i
.eq(insn
)
364 m
.next
= "INSN_READY"
366 with m
.State("INSN_READ2"):
367 with m
.If(self
.imem
.f_busy_o
): # zzz...
368 # busy: stay in wait-read
369 comb
+= self
.imem
.a_i_valid
.eq(1)
370 comb
+= self
.imem
.f_i_valid
.eq(1)
372 # not busy: instruction fetched
373 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
374 sync
+= dec_opcode_i
.eq(insn
)
375 m
.next
= "INSN_READY"
376 # TODO: probably can start looking at pdecode2.rm_dec
377 # here or maybe even in INSN_READ state, if svp64_mode
378 # detected, in order to trigger - and wait for - the
381 pmode
= pdecode2
.rm_dec
.predmode
383 if pmode != SVP64PredMode.ALWAYS.value:
384 fire predicate loading FSM and wait before
387 sync += self.srcmask.eq(-1) # set to all 1s
388 sync += self.dstmask.eq(-1) # set to all 1s
389 m.next = "INSN_READY"
392 with m
.State("INSN_READY"):
393 # hand over the instruction, to be decoded
394 comb
+= fetch_insn_o_valid
.eq(1)
395 with m
.If(fetch_insn_i_ready
):
398 def fetch_predicate_fsm(self
, m
,
399 pred_insn_i_valid
, pred_insn_o_ready
,
400 pred_mask_o_valid
, pred_mask_i_ready
):
401 """fetch_predicate_fsm - obtains (constructs in the case of CR)
402 src/dest predicate masks
404 https://bugs.libre-soc.org/show_bug.cgi?id=617
405 the predicates can be read here, by using IntRegs r_ports['pred']
406 or CRRegs r_ports['pred']. in the case of CRs it will have to
407 be done through multiple reads, extracting one relevant at a time.
408 later, a faster way would be to use the 32-bit-wide CR port but
409 this is more complex decoding, here. equivalent code used in
410 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
412 note: this ENTIRE FSM is not to be called when svp64 is disabled
416 pdecode2
= self
.pdecode2
417 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
418 predmode
= rm_dec
.predmode
419 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
420 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
421 # get src/dst step, so we can skip already used mask bits
422 cur_state
= self
.cur_state
423 srcstep
= cur_state
.svstate
.srcstep
424 dststep
= cur_state
.svstate
.dststep
425 cur_vl
= cur_state
.svstate
.vl
428 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
429 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
430 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
431 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
433 # store fetched masks, for either intpred or crpred
434 # when src/dst step is not zero, the skipped mask bits need to be
435 # shifted-out, before actually storing them in src/dest mask
436 new_srcmask
= Signal(64, reset_less
=True)
437 new_dstmask
= Signal(64, reset_less
=True)
439 with m
.FSM(name
="fetch_predicate"):
441 with m
.State("FETCH_PRED_IDLE"):
442 comb
+= pred_insn_o_ready
.eq(1)
443 with m
.If(pred_insn_i_valid
):
444 with m
.If(predmode
== SVP64PredMode
.INT
):
445 # skip fetching destination mask register, when zero
447 sync
+= new_dstmask
.eq(-1)
448 # directly go to fetch source mask register
449 # guaranteed not to be zero (otherwise predmode
450 # would be SVP64PredMode.ALWAYS, not INT)
451 comb
+= int_pred
.addr
.eq(sregread
)
452 comb
+= int_pred
.ren
.eq(1)
453 m
.next
= "INT_SRC_READ"
454 # fetch destination predicate register
456 comb
+= int_pred
.addr
.eq(dregread
)
457 comb
+= int_pred
.ren
.eq(1)
458 m
.next
= "INT_DST_READ"
459 with m
.Elif(predmode
== SVP64PredMode
.CR
):
460 # go fetch masks from the CR register file
461 sync
+= new_srcmask
.eq(0)
462 sync
+= new_dstmask
.eq(0)
465 sync
+= self
.srcmask
.eq(-1)
466 sync
+= self
.dstmask
.eq(-1)
467 m
.next
= "FETCH_PRED_DONE"
469 with m
.State("INT_DST_READ"):
470 # store destination mask
471 inv
= Repl(dinvert
, 64)
473 # set selected mask bit for 1<<r3 mode
474 dst_shift
= Signal(range(64))
475 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
476 sync
+= new_dstmask
.eq(1 << dst_shift
)
478 # invert mask if requested
479 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
480 # skip fetching source mask register, when zero
482 sync
+= new_srcmask
.eq(-1)
483 m
.next
= "FETCH_PRED_SHIFT_MASK"
484 # fetch source predicate register
486 comb
+= int_pred
.addr
.eq(sregread
)
487 comb
+= int_pred
.ren
.eq(1)
488 m
.next
= "INT_SRC_READ"
490 with m
.State("INT_SRC_READ"):
492 inv
= Repl(sinvert
, 64)
494 # set selected mask bit for 1<<r3 mode
495 src_shift
= Signal(range(64))
496 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
497 sync
+= new_srcmask
.eq(1 << src_shift
)
499 # invert mask if requested
500 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
501 m
.next
= "FETCH_PRED_SHIFT_MASK"
503 # fetch masks from the CR register file
504 # implements the following loop:
505 # idx, inv = get_predcr(mask)
507 # for cr_idx in range(vl):
508 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
510 # mask |= 1 << cr_idx
512 with m
.State("CR_READ"):
513 # CR index to be read, which will be ready by the next cycle
514 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
515 # submit the read operation to the regfile
516 with m
.If(cr_idx
!= cur_vl
):
517 # the CR read port is unary ...
519 # ... in MSB0 convention ...
520 # ren = 1 << (7 - cr_idx)
521 # ... and with an offset:
522 # ren = 1 << (7 - off - cr_idx)
523 idx
= SVP64CROffs
.CRPred
+ cr_idx
524 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
525 # signal data valid in the next cycle
526 cr_read
= Signal(reset_less
=True)
527 sync
+= cr_read
.eq(1)
528 # load the next index
529 sync
+= cr_idx
.eq(cr_idx
+ 1)
532 sync
+= cr_read
.eq(0)
534 m
.next
= "FETCH_PRED_SHIFT_MASK"
536 # compensate for the one cycle delay on the regfile
537 cur_cr_idx
= Signal
.like(cur_vl
)
538 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
539 # read the CR field, select the appropriate bit
543 comb
+= cr_field
.eq(cr_pred
.o_data
)
544 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1) ^ scrinvert
)
545 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1) ^ dcrinvert
)
546 # set the corresponding mask bit
547 bit_to_set
= Signal
.like(self
.srcmask
)
548 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
550 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
552 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
554 with m
.State("FETCH_PRED_SHIFT_MASK"):
555 # shift-out skipped mask bits
556 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
557 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
558 m
.next
= "FETCH_PRED_DONE"
560 with m
.State("FETCH_PRED_DONE"):
561 comb
+= pred_mask_o_valid
.eq(1)
562 with m
.If(pred_mask_i_ready
):
563 m
.next
= "FETCH_PRED_IDLE"
565 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
566 dbg
, core_rst
, is_svp64_mode
,
567 fetch_pc_o_ready
, fetch_pc_i_valid
,
568 fetch_insn_o_valid
, fetch_insn_i_ready
,
569 pred_insn_i_valid
, pred_insn_o_ready
,
570 pred_mask_o_valid
, pred_mask_i_ready
,
571 exec_insn_i_valid
, exec_insn_o_ready
,
572 exec_pc_o_valid
, exec_pc_i_ready
):
575 decode / issue FSM. this interacts with the "fetch" FSM
576 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
577 (outgoing). also interacts with the "execute" FSM
578 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
580 SVP64 RM prefixes have already been set up by the
581 "fetch" phase, so execute is fairly straightforward.
586 pdecode2
= self
.pdecode2
587 cur_state
= self
.cur_state
590 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
592 # for updating svstate (things like srcstep etc.)
593 update_svstate
= Signal() # set this (below) if updating
594 new_svstate
= SVSTATERec("new_svstate")
595 comb
+= new_svstate
.eq(cur_state
.svstate
)
597 # precalculate srcstep+1 and dststep+1
598 cur_srcstep
= cur_state
.svstate
.srcstep
599 cur_dststep
= cur_state
.svstate
.dststep
600 next_srcstep
= Signal
.like(cur_srcstep
)
601 next_dststep
= Signal
.like(cur_dststep
)
602 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
603 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
605 # note if an exception happened. in a pipelined or OoO design
606 # this needs to be accompanied by "shadowing" (or stalling)
607 exc_happened
= self
.core
.o
.exc_happened
609 with m
.FSM(name
="issue_fsm"):
611 # sync with the "fetch" phase which is reading the instruction
612 # at this point, there is no instruction running, that
613 # could inadvertently update the PC.
614 with m
.State("ISSUE_START"):
615 # wait on "core stop" release, before next fetch
616 # need to do this here, in case we are in a VL==0 loop
617 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
618 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
619 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
622 # tell core it's stopped, and acknowledge debug handshake
623 comb
+= dbg
.core_stopped_i
.eq(1)
624 # while stopped, allow updating the PC and SVSTATE
625 with m
.If(self
.pc_i
.ok
):
626 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
627 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
628 sync
+= pc_changed
.eq(1)
629 with m
.If(self
.svstate_i
.ok
):
630 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
631 comb
+= update_svstate
.eq(1)
632 sync
+= sv_changed
.eq(1)
634 # wait for an instruction to arrive from Fetch
635 with m
.State("INSN_WAIT"):
636 comb
+= fetch_insn_i_ready
.eq(1)
637 with m
.If(fetch_insn_o_valid
):
638 # loop into ISSUE_START if it's a SVP64 instruction
639 # and VL == 0. this because VL==0 is a for-loop
640 # from 0 to 0 i.e. always, always a NOP.
641 cur_vl
= cur_state
.svstate
.vl
642 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
643 # update the PC before fetching the next instruction
644 # since we are in a VL==0 loop, no instruction was
645 # executed that we could be overwriting
646 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
647 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
648 comb
+= self
.insn_done
.eq(1)
649 m
.next
= "ISSUE_START"
652 m
.next
= "PRED_START" # start fetching predicate
654 m
.next
= "DECODE_SV" # skip predication
656 with m
.State("PRED_START"):
657 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
658 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
661 with m
.State("MASK_WAIT"):
662 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
663 with m
.If(pred_mask_o_valid
): # predication masks are ready
666 # skip zeros in predicate
667 with m
.State("PRED_SKIP"):
668 with m
.If(~is_svp64_mode
):
669 m
.next
= "DECODE_SV" # nothing to do
672 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
673 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
675 # new srcstep, after skipping zeros
676 skip_srcstep
= Signal
.like(cur_srcstep
)
677 # value to be added to the current srcstep
678 src_delta
= Signal
.like(cur_srcstep
)
679 # add leading zeros to srcstep, if not in zero mode
680 with m
.If(~pred_src_zero
):
681 # priority encoder (count leading zeros)
682 # append guard bit, in case the mask is all zeros
683 pri_enc_src
= PriorityEncoder(65)
684 m
.submodules
.pri_enc_src
= pri_enc_src
685 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
687 comb
+= src_delta
.eq(pri_enc_src
.o
)
688 # apply delta to srcstep
689 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
690 # shift-out all leading zeros from the mask
691 # plus the leading "one" bit
692 # TODO count leading zeros and shift-out the zero
693 # bits, in the same step, in hardware
694 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
696 # same as above, but for dststep
697 skip_dststep
= Signal
.like(cur_dststep
)
698 dst_delta
= Signal
.like(cur_dststep
)
699 with m
.If(~pred_dst_zero
):
700 pri_enc_dst
= PriorityEncoder(65)
701 m
.submodules
.pri_enc_dst
= pri_enc_dst
702 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
704 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
705 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
706 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
708 # TODO: initialize mask[VL]=1 to avoid passing past VL
709 with m
.If((skip_srcstep
>= cur_vl
) |
710 (skip_dststep
>= cur_vl
)):
711 # end of VL loop. Update PC and reset src/dst step
712 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
713 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
714 comb
+= new_svstate
.srcstep
.eq(0)
715 comb
+= new_svstate
.dststep
.eq(0)
716 comb
+= update_svstate
.eq(1)
717 # synchronize with the simulator
718 comb
+= self
.insn_done
.eq(1)
720 m
.next
= "ISSUE_START"
722 # update new src/dst step
723 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
724 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
725 comb
+= update_svstate
.eq(1)
729 # pass predicate mask bits through to satellite decoders
730 # TODO: for SIMD this will be *multiple* bits
731 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
732 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
734 # after src/dst step have been updated, we are ready
735 # to decode the instruction
736 with m
.State("DECODE_SV"):
737 # decode the instruction
738 sync
+= core
.i
.e
.eq(pdecode2
.e
)
739 sync
+= core
.i
.state
.eq(cur_state
)
740 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
741 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
743 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
744 # set RA_OR_ZERO detection in satellite decoders
745 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
746 # and svp64 detection
747 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
748 # and svp64 bit-rev'd ldst mode
749 ldst_dec
= pdecode2
.use_svp64_ldst_dec
750 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
751 # after decoding, reset any previous exception condition,
752 # allowing it to be set again during the next execution
753 sync
+= pdecode2
.ldst_exc
.eq(0)
755 m
.next
= "INSN_EXECUTE" # move to "execute"
757 # handshake with execution FSM, move to "wait" once acknowledged
758 with m
.State("INSN_EXECUTE"):
759 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
760 with m
.If(exec_insn_o_ready
): # execute acknowledged us
761 m
.next
= "EXECUTE_WAIT"
763 with m
.State("EXECUTE_WAIT"):
764 # wait on "core stop" release, at instruction end
765 # need to do this here, in case we are in a VL>1 loop
766 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
767 comb
+= exec_pc_i_ready
.eq(1)
768 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
769 # the exception info needs to be blatted into
770 # pdecode.ldst_exc, and the instruction "re-run".
771 # when ldst_exc.happened is set, the PowerDecoder2
772 # reacts very differently: it re-writes the instruction
773 # with a "trap" (calls PowerDecoder2.trap()) which
774 # will *overwrite* whatever was requested and jump the
775 # PC to the exception address, as well as alter MSR.
776 # nothing else needs to be done other than to note
777 # the change of PC and MSR (and, later, SVSTATE)
778 with m
.If(exc_happened
):
779 sync
+= pdecode2
.ldst_exc
.eq(core
.fus
.get_exc("ldst0"))
781 with m
.If(exec_pc_o_valid
):
783 # was this the last loop iteration?
785 cur_vl
= cur_state
.svstate
.vl
786 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
788 # return directly to Decode if Execute generated an
790 with m
.If(pdecode2
.ldst_exc
.happened
):
793 # if either PC or SVSTATE were changed by the previous
794 # instruction, go directly back to Fetch, without
795 # updating either PC or SVSTATE
796 with m
.Elif(pc_changed | sv_changed
):
797 m
.next
= "ISSUE_START"
799 # also return to Fetch, when no output was a vector
800 # (regardless of SRCSTEP and VL), or when the last
801 # instruction was really the last one of the VL loop
802 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
803 # before going back to fetch, update the PC state
804 # register with the NIA.
805 # ok here we are not reading the branch unit.
806 # TODO: this just blithely overwrites whatever
807 # pipeline updated the PC
808 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
809 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
810 # reset SRCSTEP before returning to Fetch
812 with m
.If(pdecode2
.loop_continue
):
813 comb
+= new_svstate
.srcstep
.eq(0)
814 comb
+= new_svstate
.dststep
.eq(0)
815 comb
+= update_svstate
.eq(1)
817 comb
+= new_svstate
.srcstep
.eq(0)
818 comb
+= new_svstate
.dststep
.eq(0)
819 comb
+= update_svstate
.eq(1)
820 m
.next
= "ISSUE_START"
822 # returning to Execute? then, first update SRCSTEP
824 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
825 comb
+= new_svstate
.dststep
.eq(next_dststep
)
826 comb
+= update_svstate
.eq(1)
827 # return to mask skip loop
831 comb
+= dbg
.core_stopped_i
.eq(1)
832 # while stopped, allow updating the PC and SVSTATE
833 with m
.If(self
.pc_i
.ok
):
834 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
835 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
836 sync
+= pc_changed
.eq(1)
837 with m
.If(self
.svstate_i
.ok
):
838 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
839 comb
+= update_svstate
.eq(1)
840 sync
+= sv_changed
.eq(1)
842 # check if svstate needs updating: if so, write it to State Regfile
843 with m
.If(update_svstate
):
844 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
845 comb
+= self
.state_w_sv
.i_data
.eq(new_svstate
)
846 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
848 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
849 exec_insn_i_valid
, exec_insn_o_ready
,
850 exec_pc_o_valid
, exec_pc_i_ready
):
853 execute FSM. this interacts with the "issue" FSM
854 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
855 (outgoing). SVP64 RM prefixes have already been set up by the
856 "issue" phase, so execute is fairly straightforward.
861 pdecode2
= self
.pdecode2
864 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
865 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
867 with m
.FSM(name
="exec_fsm"):
869 # waiting for instruction bus (stays there until not busy)
870 with m
.State("INSN_START"):
871 comb
+= exec_insn_o_ready
.eq(1)
872 with m
.If(exec_insn_i_valid
):
873 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
874 sync
+= sv_changed
.eq(0)
875 sync
+= pc_changed
.eq(0)
876 m
.next
= "INSN_ACTIVE" # move to "wait completion"
878 # instruction started: must wait till it finishes
879 with m
.State("INSN_ACTIVE"):
880 # note changes to PC and SVSTATE
881 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
882 sync
+= sv_changed
.eq(1)
883 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
884 sync
+= pc_changed
.eq(1)
885 with m
.If(~core_busy_o
): # instruction done!
886 comb
+= exec_pc_o_valid
.eq(1)
887 with m
.If(exec_pc_i_ready
):
888 # when finished, indicate "done".
889 # however, if there was an exception, the instruction
890 # is *not* yet done. this is an implementation
891 # detail: we choose to implement exceptions by
892 # taking the exception information from the LDST
893 # unit, putting that *back* into the PowerDecoder2,
894 # and *re-running the entire instruction*.
895 # if we erroneously indicate "done" here, it is as if
896 # there were *TWO* instructions:
897 # 1) the failed LDST 2) a TRAP.
898 with m
.If(~pdecode2
.ldst_exc
.happened
):
899 comb
+= self
.insn_done
.eq(1)
900 m
.next
= "INSN_START" # back to fetch
902 def setup_peripherals(self
, m
):
903 comb
, sync
= m
.d
.comb
, m
.d
.sync
905 # okaaaay so the debug module must be in coresync clock domain
906 # but NOT its reset signal. to cope with this, set every single
907 # submodule explicitly in coresync domain, debug and JTAG
908 # in their own one but using *external* reset.
909 csd
= DomainRenamer("coresync")
910 dbd
= DomainRenamer(self
.dbg_domain
)
912 m
.submodules
.core
= core
= csd(self
.core
)
913 m
.submodules
.imem
= imem
= csd(self
.imem
)
914 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
916 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
917 # TODO: UART2GDB mux, here, from external pin
918 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
919 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
921 cur_state
= self
.cur_state
923 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
925 for i
, sram
in enumerate(self
.sram4k
):
926 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
927 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
929 # XICS interrupt handler
931 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
932 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
933 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
934 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
936 # GPIO test peripheral
938 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
940 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
941 # XXX causes litex ECP5 test to get wrong idea about input and output
942 # (but works with verilator sim *sigh*)
943 #if self.gpio and self.xics:
944 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
946 # instruction decoder
947 pdecode
= create_pdecode()
948 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
950 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
953 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
954 intrf
= self
.core
.regs
.rf
['int']
956 # clock delay power-on reset
957 cd_por
= ClockDomain(reset_less
=True)
958 cd_sync
= ClockDomain()
959 core_sync
= ClockDomain("coresync")
960 m
.domains
+= cd_por
, cd_sync
, core_sync
961 if self
.dbg_domain
!= "sync":
962 dbg_sync
= ClockDomain(self
.dbg_domain
)
963 m
.domains
+= dbg_sync
965 ti_rst
= Signal(reset_less
=True)
966 delay
= Signal(range(4), reset
=3)
967 with m
.If(delay
!= 0):
968 m
.d
.por
+= delay
.eq(delay
- 1)
969 comb
+= cd_por
.clk
.eq(ClockSignal())
971 # power-on reset delay
972 core_rst
= ResetSignal("coresync")
973 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
974 comb
+= core_rst
.eq(ti_rst
)
976 # debug clock is same as coresync, but reset is *main external*
977 if self
.dbg_domain
!= "sync":
978 dbg_rst
= ResetSignal(self
.dbg_domain
)
979 comb
+= dbg_rst
.eq(ResetSignal())
981 # busy/halted signals from core
982 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
983 comb
+= self
.busy_o
.eq(core_busy_o
)
984 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
986 # temporary hack: says "go" immediately for both address gen and ST
988 ldst
= core
.fus
.fus
['ldst0']
989 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
990 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
991 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
993 def elaborate(self
, platform
):
996 comb
, sync
= m
.d
.comb
, m
.d
.sync
997 cur_state
= self
.cur_state
998 pdecode2
= self
.pdecode2
1002 # set up peripherals and core
1003 core_rst
= self
.core_rst
1004 self
.setup_peripherals(m
)
1006 # reset current state if core reset requested
1007 with m
.If(core_rst
):
1008 m
.d
.sync
+= self
.cur_state
.eq(0)
1010 # PC and instruction from I-Memory
1011 comb
+= self
.pc_o
.eq(cur_state
.pc
)
1012 pc_changed
= Signal() # note write to PC
1013 sv_changed
= Signal() # note write to SVSTATE
1015 # read state either from incoming override or from regfile
1016 # TODO: really should be doing MSR in the same way
1017 pc
= state_get(m
, core_rst
, self
.pc_i
,
1019 self
.state_r_pc
, StateRegs
.PC
)
1020 svstate
= state_get(m
, core_rst
, self
.svstate_i
,
1021 "svstate", # read SVSTATE
1022 self
.state_r_sv
, StateRegs
.SVSTATE
)
1024 # don't write pc every cycle
1025 comb
+= self
.state_w_pc
.wen
.eq(0)
1026 comb
+= self
.state_w_pc
.i_data
.eq(0)
1028 # don't read msr every cycle
1029 comb
+= self
.state_r_msr
.ren
.eq(0)
1031 # address of the next instruction, in the absence of a branch
1032 # depends on the instruction size
1035 # connect up debug signals
1036 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
1037 comb
+= dbg
.terminate_i
.eq(core
.o
.core_terminate_o
)
1038 comb
+= dbg
.state
.pc
.eq(pc
)
1039 comb
+= dbg
.state
.svstate
.eq(svstate
)
1040 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
1042 # pass the prefix mode from Fetch to Issue, so the latter can loop
1044 is_svp64_mode
= Signal()
1046 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1047 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1048 # these are the handshake signals between each
1050 # fetch FSM can run as soon as the PC is valid
1051 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1052 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1054 # fetch FSM hands over the instruction to be decoded / issued
1055 fetch_insn_o_valid
= Signal()
1056 fetch_insn_i_ready
= Signal()
1058 # predicate fetch FSM decodes and fetches the predicate
1059 pred_insn_i_valid
= Signal()
1060 pred_insn_o_ready
= Signal()
1062 # predicate fetch FSM delivers the masks
1063 pred_mask_o_valid
= Signal()
1064 pred_mask_i_ready
= Signal()
1066 # issue FSM delivers the instruction to the be executed
1067 exec_insn_i_valid
= Signal()
1068 exec_insn_o_ready
= Signal()
1070 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1071 exec_pc_o_valid
= Signal()
1072 exec_pc_i_ready
= Signal()
1074 # the FSMs here are perhaps unusual in that they detect conditions
1075 # then "hold" information, combinatorially, for the core
1076 # (as opposed to using sync - which would be on a clock's delay)
1077 # this includes the actual opcode, valid flags and so on.
1079 # Fetch, then predicate fetch, then Issue, then Execute.
1080 # Issue is where the VL for-loop # lives. the ready/valid
1081 # signalling is used to communicate between the four.
1083 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
1084 fetch_pc_o_ready
, fetch_pc_i_valid
,
1085 fetch_insn_o_valid
, fetch_insn_i_ready
)
1087 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
1088 dbg
, core_rst
, is_svp64_mode
,
1089 fetch_pc_o_ready
, fetch_pc_i_valid
,
1090 fetch_insn_o_valid
, fetch_insn_i_ready
,
1091 pred_insn_i_valid
, pred_insn_o_ready
,
1092 pred_mask_o_valid
, pred_mask_i_ready
,
1093 exec_insn_i_valid
, exec_insn_o_ready
,
1094 exec_pc_o_valid
, exec_pc_i_ready
)
1097 self
.fetch_predicate_fsm(m
,
1098 pred_insn_i_valid
, pred_insn_o_ready
,
1099 pred_mask_o_valid
, pred_mask_i_ready
)
1101 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
1102 exec_insn_i_valid
, exec_insn_o_ready
,
1103 exec_pc_o_valid
, exec_pc_i_ready
)
1105 # whatever was done above, over-ride it if core reset is held
1106 with m
.If(core_rst
):
1109 # this bit doesn't have to be in the FSM: connect up to read
1110 # regfiles on demand from DMI
1113 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
1114 # (which uses that in PowerDecoder2 to raise 0x900 exception)
1115 self
.tb_dec_fsm(m
, cur_state
.dec
)
1119 def do_dmi(self
, m
, dbg
):
1120 """deals with DMI debug requests
1122 currently only provides read requests for the INT regfile, CR and XER
1123 it will later also deal with *writing* to these regfiles.
1127 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
1128 intrf
= self
.core
.regs
.rf
['int']
1130 with m
.If(d_reg
.req
): # request for regfile access being made
1131 # TODO: error-check this
1132 # XXX should this be combinatorial? sync better?
1134 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
1136 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
1137 comb
+= self
.int_r
.ren
.eq(1)
1138 d_reg_delay
= Signal()
1139 sync
+= d_reg_delay
.eq(d_reg
.req
)
1140 with m
.If(d_reg_delay
):
1141 # data arrives one clock later
1142 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
1143 comb
+= d_reg
.ack
.eq(1)
1145 # sigh same thing for CR debug
1146 with m
.If(d_cr
.req
): # request for regfile access being made
1147 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
1148 d_cr_delay
= Signal()
1149 sync
+= d_cr_delay
.eq(d_cr
.req
)
1150 with m
.If(d_cr_delay
):
1151 # data arrives one clock later
1152 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
1153 comb
+= d_cr
.ack
.eq(1)
1156 with m
.If(d_xer
.req
): # request for regfile access being made
1157 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
1158 d_xer_delay
= Signal()
1159 sync
+= d_xer_delay
.eq(d_xer
.req
)
1160 with m
.If(d_xer_delay
):
1161 # data arrives one clock later
1162 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
1163 comb
+= d_xer
.ack
.eq(1)
1165 def tb_dec_fsm(self
, m
, spr_dec
):
1168 this is a FSM for updating either dec or tb. it runs alternately
1169 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1170 value to DEC, however the regfile has "passthrough" on it so this
1173 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1176 comb
, sync
= m
.d
.comb
, m
.d
.sync
1177 fast_rf
= self
.core
.regs
.rf
['fast']
1178 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
1179 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
1181 with m
.FSM() as fsm
:
1183 # initiates read of current DEC
1184 with m
.State("DEC_READ"):
1185 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
1186 comb
+= fast_r_dectb
.ren
.eq(1)
1187 m
.next
= "DEC_WRITE"
1189 # waits for DEC read to arrive (1 cycle), updates with new value
1190 with m
.State("DEC_WRITE"):
1191 new_dec
= Signal(64)
1192 # TODO: MSR.LPCR 32-bit decrement mode
1193 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
1194 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
1195 comb
+= fast_w_dectb
.wen
.eq(1)
1196 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
1197 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
1200 # initiates read of current TB
1201 with m
.State("TB_READ"):
1202 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
1203 comb
+= fast_r_dectb
.ren
.eq(1)
1206 # waits for read TB to arrive, initiates write of current TB
1207 with m
.State("TB_WRITE"):
1209 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
1210 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
1211 comb
+= fast_w_dectb
.wen
.eq(1)
1212 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
1218 yield from self
.pc_i
.ports()
1221 yield from self
.core
.ports()
1222 yield from self
.imem
.ports()
1223 yield self
.core_bigendian_i
1229 def external_ports(self
):
1230 ports
= self
.pc_i
.ports()
1231 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
1235 ports
+= list(self
.jtag
.external_ports())
1237 # don't add DMI if JTAG is enabled
1238 ports
+= list(self
.dbg
.dmi
.ports())
1240 ports
+= list(self
.imem
.ibus
.fields
.values())
1241 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
1244 for sram
in self
.sram4k
:
1245 ports
+= list(sram
.bus
.fields
.values())
1248 ports
+= list(self
.xics_icp
.bus
.fields
.values())
1249 ports
+= list(self
.xics_ics
.bus
.fields
.values())
1250 ports
.append(self
.int_level_i
)
1253 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
1254 ports
.append(self
.gpio_o
)
1262 class TestIssuer(Elaboratable
):
1263 def __init__(self
, pspec
):
1264 self
.ti
= TestIssuerInternal(pspec
)
1265 self
.pll
= DummyPLL(instance
=True)
1267 # PLL direct clock or not
1268 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1270 self
.pll_test_o
= Signal(reset_less
=True)
1271 self
.pll_vco_o
= Signal(reset_less
=True)
1272 self
.clk_sel_i
= Signal(2, reset_less
=True)
1273 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1274 self
.pllclk_clk
= ClockSignal("pllclk")
1276 def elaborate(self
, platform
):
1280 # TestIssuer nominally runs at main clock, actually it is
1281 # all combinatorial internally except for coresync'd components
1282 m
.submodules
.ti
= ti
= self
.ti
1285 # ClockSelect runs at PLL output internal clock rate
1286 m
.submodules
.wrappll
= pll
= self
.pll
1288 # add clock domains from PLL
1289 cd_pll
= ClockDomain("pllclk")
1292 # PLL clock established. has the side-effect of running clklsel
1293 # at the PLL's speed (see DomainRenamer("pllclk") above)
1294 pllclk
= self
.pllclk_clk
1295 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1297 # wire up external 24mhz to PLL
1298 #comb += pll.clk_24_i.eq(self.ref_clk)
1299 # output 18 mhz PLL test signal, and analog oscillator out
1300 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1301 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1303 # input to pll clock selection
1304 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1306 # now wire up ResetSignals. don't mind them being in this domain
1307 pll_rst
= ResetSignal("pllclk")
1308 comb
+= pll_rst
.eq(ResetSignal())
1310 # internal clock is set to selector clock-out. has the side-effect of
1311 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1312 # debug clock runs at coresync internal clock
1313 cd_coresync
= ClockDomain("coresync")
1314 #m.domains += cd_coresync
1315 if self
.ti
.dbg_domain
!= 'sync':
1316 cd_dbgsync
= ClockDomain("dbgsync")
1317 #m.domains += cd_dbgsync
1318 intclk
= ClockSignal("coresync")
1319 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1320 # XXX BYPASS PLL XXX
1321 # XXX BYPASS PLL XXX
1322 # XXX BYPASS PLL XXX
1324 comb
+= intclk
.eq(self
.ref_clk
)
1326 comb
+= intclk
.eq(ClockSignal())
1327 if self
.ti
.dbg_domain
!= 'sync':
1328 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1329 comb
+= dbgclk
.eq(intclk
)
1334 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1335 [ClockSignal(), ResetSignal()]
1337 def external_ports(self
):
1338 ports
= self
.ti
.external_ports()
1339 ports
.append(ClockSignal())
1340 ports
.append(ResetSignal())
1342 ports
.append(self
.clk_sel_i
)
1343 ports
.append(self
.pll
.clk_24_i
)
1344 ports
.append(self
.pll_test_o
)
1345 ports
.append(self
.pll_vco_o
)
1346 ports
.append(self
.pllclk_clk
)
1347 ports
.append(self
.ref_clk
)
1351 if __name__
== '__main__':
1352 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1358 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1359 imem_ifacetype
='bare_wb',
1364 dut
= TestIssuer(pspec
)
1365 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1367 if len(sys
.argv
) == 1:
1368 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1369 with
open("test_issuer.il", "w") as f
: