src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20
  21 from soc.decoder.decode2execute1 import Data
  22 from soc.experiment.testmem import TestMemory # test only for instructions
  23 from soc.regfile.regfiles import FastRegs
  24 from soc.simple.core import NonProductionCore
  25 from soc.config.test.test_loadstore import TestMemPspec
  26 from soc.config.ifetch import ConfigFetchUnit
  27 from soc.decoder.power_enums import MicrOp
  28
  29
  30 class TestIssuer(Elaboratable):
  31     """TestIssuer - reads instructions from TestMemory and issues them
  32
  33     efficiency and speed is not the main goal here: functional correctness is.
  34     """
  35     def __init__(self, pspec):
  36         # main instruction core
  37         self.core = core = NonProductionCore(pspec)
  38
  39         # Test Instruction memory
  40         self.imem = ConfigFetchUnit(pspec).fu
  41         # one-row cache of instruction read
  42         self.iline = Signal(64) # one instruction line
  43         self.iprev_adr = Signal(64) # previous address: if different, do read
  44
  45         # instruction go/monitor
  46         self.go_insn_i = Signal(reset_less=True)
  47         self.pc_o = Signal(64, reset_less=True)
  48         self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
  49         self.busy_o = core.busy_o
  50         self.memerr_o = Signal(reset_less=True)
  51
  52         # FAST regfile read /write ports for PC and MSR
  53         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['d_rd1'] # PC rd
  54         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  55         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['d_rd2'] # MSR rd
  56
  57         # hack method of keeping an eye on whether branch/trap set the PC
  58         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  59         self.fast_nia.wen.name = 'fast_nia_wen'
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63         comb, sync = m.d.comb, m.d.sync
  64
  65         m.submodules.core = core = self.core
  66         m.submodules.imem = imem = self.imem
  67
  68         # temporary hack: says "go" immediately for both address gen and ST
  69         l0 = core.l0
  70         ldst = core.fus.fus['ldst0']
  71         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  72         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  73
  74         # PC and instruction from I-Memory
  75         current_insn = Signal(32) # current fetched instruction (note sync)
  76         cur_pc = Signal(64) # current PC (note it is reset/sync)
  77         pc_changed = Signal() # note write to PC
  78         comb += self.pc_o.eq(cur_pc)
  79         ilatch = Signal(32)
  80
  81         # MSR (temp and latched)
  82         cur_msr = Signal(64) # current MSR (note it is reset/sync)
  83         msr = Signal(64, reset_less=True)
  84
  85         # next instruction (+4 on current)
  86         nia = Signal(64, reset_less=True)
  87         comb += nia.eq(cur_pc + 4)
  88
  89         # temporaries
  90         core_busy_o = core.busy_o         # core is busy
  91         core_ivalid_i = core.ivalid_i     # instruction is valid
  92         core_issue_i = core.issue_i       # instruction is issued
  93         core_be_i = core.bigendian_i      # bigendian mode
  94         core_opcode_i = core.raw_opcode_i # raw opcode
  95
  96         insn_type = core.pdecode2.e.do.insn_type
  97         insn_msr = core.pdecode2.msr
  98
  99         # only run if not in halted state
 100         with m.If(~core.core_terminated_o):
 101
 102             # actually use a nmigen FSM for the first time (w00t)
 103             # this FSM is perhaps unusual in that it detects conditions
 104             # then "holds" information, combinatorially, for the core
 105             # (as opposed to using sync - which would be on a clock's delay)
 106             # this includes the actual opcode, valid flags and so on.
 107             with m.FSM() as fsm:
 108
 109                 # waiting (zzz)
 110                 with m.State("IDLE"):
 111                     sync += pc_changed.eq(0)
 112                     with m.If(self.go_insn_i):
 113                         # instruction allowed to go: start by reading the PC
 114                         pc = Signal(64, reset_less=True)
 115                         with m.If(self.pc_i.ok):
 116                             # incoming override (start from pc_i)
 117                             comb += pc.eq(self.pc_i.data)
 118                         with m.Else():
 119                             # otherwise read FastRegs regfile for PC
 120                             comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 121                             comb += pc.eq(self.fast_r_pc.data_o)
 122                         # capture the PC and also drop it into Insn Memory
 123                         # we have joined a pair of combinatorial memory
 124                         # lookups together.  this is Generally Bad.
 125                         comb += self.imem.a_pc_i.eq(pc)
 126                         comb += self.imem.a_valid_i.eq(1)
 127                         comb += self.imem.f_valid_i.eq(1)
 128                         sync += cur_pc.eq(pc)
 129                         m.next = "INSN_READ" # move to "wait for bus" phase
 130
 131                 # waiting for instruction bus (stays there until not busy)
 132                 with m.State("INSN_READ"):
 133                     with m.If(self.imem.f_busy_o): # zzz...
 134                         # busy: stay in wait-read
 135                         comb += self.imem.a_valid_i.eq(1)
 136                         comb += self.imem.f_valid_i.eq(1)
 137                     with m.Else():
 138                         # not busy: instruction fetched
 139                         insn = self.imem.f_instr_o.word_select(cur_pc[2], 32)
 140                         comb += current_insn.eq(insn)
 141                         comb += core_ivalid_i.eq(1) # instruction is valid
 142                         comb += core_issue_i.eq(1)  # and issued
 143                         comb += core_opcode_i.eq(current_insn) # actual opcode
 144                         sync += ilatch.eq(current_insn) # latch current insn
 145
 146                         # read MSR
 147                         comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 148                         comb += msr.eq(self.fast_r_msr.data_o)
 149                         comb += insn_msr.eq(msr)
 150                         sync += cur_msr.eq(msr) # latch current MSR
 151
 152                         m.next = "INSN_ACTIVE" # move to "wait completion"
 153
 154                 # instruction started: must wait till it finishes
 155                 with m.State("INSN_ACTIVE"):
 156                     with m.If(core.core_terminated_o):
 157                         m.next = "IDLE" # back to idle, immediately (OP_ATTN)
 158                     with m.Else():
 159                         with m.If(insn_type != MicrOp.OP_NOP):
 160                             comb += core_ivalid_i.eq(1) # instruction is valid
 161                         comb += core_opcode_i.eq(ilatch) # actual opcode
 162                         comb += insn_msr.eq(cur_msr)     # and MSR
 163                         with m.If(self.fast_nia.wen):
 164                             sync += pc_changed.eq(1)
 165                         with m.If(~core_busy_o): # instruction done!
 166                             # ok here we are not reading the branch unit.  TODO
 167                             # this just blithely overwrites whatever pipeline
 168                             # updated the PC
 169                             with m.If(~pc_changed):
 170                                 comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 171                                 comb += self.fast_w_pc.data_i.eq(nia)
 172                             m.next = "IDLE" # back to idle
 173
 174         return m
 175
 176     def __iter__(self):
 177         yield from self.pc_i.ports()
 178         yield self.pc_o
 179         yield self.go_insn_i
 180         yield self.memerr_o
 181         yield from self.core.ports()
 182         yield from self.imem.ports()
 183
 184     def ports(self):
 185         return list(self)
 186
 187
 188 if __name__ == '__main__':
 189     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 190              'spr': 1,
 191              'mul': 1,
 192              'shiftrot': 1}
 193     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 194                          imem_ifacetype='bare_wb',
 195                          addr_wid=48,
 196                          mask_wid=8,
 197                          reg_wid=64,
 198                          units=units)
 199     dut = TestIssuer(pspec)
 200     vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
 201     with open("test_issuer.il", "w") as f:
 202         f.write(vl)
 203