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Decode and fetch integer predicate registers
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from soc.decoder.power_decoder import create_pdecode
25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
27 from soc.decoder.decode2execute1 import Data
28 from soc.experiment.testmem import TestMemory # test only for instructions
29 from soc.regfile.regfiles import StateRegs, FastRegs
30 from soc.simple.core import NonProductionCore
31 from soc.config.test.test_loadstore import TestMemPspec
32 from soc.config.ifetch import ConfigFetchUnit
33 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
34 SVP64PredMode)
35 from soc.debug.dmi import CoreDebug, DMIInterface
36 from soc.debug.jtag import JTAG
37 from soc.config.pinouts import get_pinspecs
38 from soc.config.state import CoreState
39 from soc.interrupts.xics import XICS_ICP, XICS_ICS
40 from soc.bus.simple_gpio import SimpleGPIO
41 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
42 from soc.clock.select import ClockSelect
43 from soc.clock.dummypll import DummyPLL
44 from soc.sv.svstate import SVSTATERec
45
46
47 from nmutil.util import rising_edge
48
49 def get_insn(f_instr_o, pc):
50 if f_instr_o.width == 32:
51 return f_instr_o
52 else:
53 # 64-bit: bit 2 of pc decides which word to select
54 return f_instr_o.word_select(pc[2], 32)
55
56 # gets state input or reads from state regfile
57 def state_get(m, state_i, name, regfile, regnum):
58 comb = m.d.comb
59 sync = m.d.sync
60 # read the PC
61 res = Signal(64, reset_less=True, name=name)
62 res_ok_delay = Signal(name="%s_ok_delay" % name)
63 sync += res_ok_delay.eq(~state_i.ok)
64 with m.If(state_i.ok):
65 # incoming override (start from pc_i)
66 comb += res.eq(state_i.data)
67 with m.Else():
68 # otherwise read StateRegs regfile for PC...
69 comb += regfile.ren.eq(1<<regnum)
70 # ... but on a 1-clock delay
71 with m.If(res_ok_delay):
72 comb += res.eq(regfile.data_o)
73 return res
74
75 def get_predint(m, mask, name):
76 """decode SVP64 predicate integer mask field to reg number and invert
77 this is identical to the equivalent function in ISACaller except that
78 it doesn't read the INT directly, it just decodes "what needs to be done"
79 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
80 """
81 comb = m.d.comb
82 regread = Signal(5, name=name+"regread")
83 invert = Signal(name=name+"invert")
84 unary = Signal(name=name+"unary")
85 with m.Switch(mask):
86 with m.Case(SVP64PredInt.ALWAYS.value):
87 comb += regread.eq(0)
88 comb += invert.eq(1)
89 with m.Case(SVP64PredInt.R3_UNARY.value):
90 comb += regread.eq(3)
91 comb += unary.eq(1)
92 with m.Case(SVP64PredInt.R3.value):
93 comb += regread.eq(3)
94 with m.Case(SVP64PredInt.R3_N.value):
95 comb += regread.eq(3)
96 comb += invert.eq(1)
97 with m.Case(SVP64PredInt.R10.value):
98 comb += regread.eq(10)
99 with m.Case(SVP64PredInt.R10_N.value):
100 comb += regread.eq(10)
101 comb += invert.eq(1)
102 with m.Case(SVP64PredInt.R30.value):
103 comb += regread.eq(30)
104 with m.Case(SVP64PredInt.R30_N.value):
105 comb += regread.eq(30)
106 comb += invert.eq(1)
107 return regread, invert, unary
108
109 def get_predcr(m, mask, name):
110 """decode SVP64 predicate CR to reg number field and invert status
111 this is identical to _get_predcr in ISACaller
112 """
113 comb = m.d.comb
114 idx = Signal(2, name=name+"idx")
115 invert = Signal(name=name+"crinvert")
116 with m.Switch(mask):
117 with m.Case(SVP64PredCR.LT.value):
118 comb += idx.eq(0)
119 comb += invert.eq(1)
120 with m.Case(SVP64PredCR.GE.value):
121 comb += idx.eq(0)
122 comb += invert.eq(0)
123 with m.Case(SVP64PredCR.GT.value):
124 comb += idx.eq(1)
125 comb += invert.eq(1)
126 with m.Case(SVP64PredCR.LE.value):
127 comb += idx.eq(1)
128 comb += invert.eq(0)
129 with m.Case(SVP64PredCR.EQ.value):
130 comb += idx.eq(2)
131 comb += invert.eq(1)
132 with m.Case(SVP64PredCR.NE.value):
133 comb += idx.eq(1)
134 comb += invert.eq(0)
135 with m.Case(SVP64PredCR.SO.value):
136 comb += idx.eq(3)
137 comb += invert.eq(1)
138 with m.Case(SVP64PredCR.NS.value):
139 comb += idx.eq(3)
140 comb += invert.eq(0)
141 return idx, invert
142
143
144 class TestIssuerInternal(Elaboratable):
145 """TestIssuer - reads instructions from TestMemory and issues them
146
147 efficiency and speed is not the main goal here: functional correctness
148 and code clarity is. optimisations (which almost 100% interfere with
149 easy understanding) come later.
150 """
151 def __init__(self, pspec):
152
153 # test is SVP64 is to be enabled
154 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
155
156 # JTAG interface. add this right at the start because if it's
157 # added it *modifies* the pspec, by adding enable/disable signals
158 # for parts of the rest of the core
159 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
160 if self.jtag_en:
161 subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
162 'pwm', 'sd0', 'sdr'}
163 self.jtag = JTAG(get_pinspecs(subset=subset))
164 # add signals to pspec to enable/disable icache and dcache
165 # (or data and intstruction wishbone if icache/dcache not included)
166 # https://bugs.libre-soc.org/show_bug.cgi?id=520
167 # TODO: do we actually care if these are not domain-synchronised?
168 # honestly probably not.
169 pspec.wb_icache_en = self.jtag.wb_icache_en
170 pspec.wb_dcache_en = self.jtag.wb_dcache_en
171 self.wb_sram_en = self.jtag.wb_sram_en
172 else:
173 self.wb_sram_en = Const(1)
174
175 # add 4k sram blocks?
176 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
177 pspec.sram4x4kblock == True)
178 if self.sram4x4k:
179 self.sram4k = []
180 for i in range(4):
181 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
182 features={'err'}))
183
184 # add interrupt controller?
185 self.xics = hasattr(pspec, "xics") and pspec.xics == True
186 if self.xics:
187 self.xics_icp = XICS_ICP()
188 self.xics_ics = XICS_ICS()
189 self.int_level_i = self.xics_ics.int_level_i
190
191 # add GPIO peripheral?
192 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
193 if self.gpio:
194 self.simple_gpio = SimpleGPIO()
195 self.gpio_o = self.simple_gpio.gpio_o
196
197 # main instruction core. suitable for prototyping / demo only
198 self.core = core = NonProductionCore(pspec)
199
200 # instruction decoder. goes into Trap Record
201 pdecode = create_pdecode()
202 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
203 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
204 opkls=IssuerDecode2ToOperand,
205 svp64_en=self.svp64_en)
206 if self.svp64_en:
207 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
208
209 # Test Instruction memory
210 self.imem = ConfigFetchUnit(pspec).fu
211
212 # DMI interface
213 self.dbg = CoreDebug()
214
215 # instruction go/monitor
216 self.pc_o = Signal(64, reset_less=True)
217 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
218 self.svstate_i = Data(32, "svstate_i") # ditto
219 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
220 self.busy_o = Signal(reset_less=True)
221 self.memerr_o = Signal(reset_less=True)
222
223 # STATE regfile read /write ports for PC, MSR, SVSTATE
224 staterf = self.core.regs.rf['state']
225 self.state_r_pc = staterf.r_ports['cia'] # PC rd
226 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
227 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
228 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
229 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
230
231 # DMI interface access
232 intrf = self.core.regs.rf['int']
233 crrf = self.core.regs.rf['cr']
234 xerrf = self.core.regs.rf['xer']
235 self.int_r = intrf.r_ports['dmi'] # INT read
236 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
237 self.xer_r = xerrf.r_ports['full_xer'] # XER read
238
239 # for predication
240 self.int_pred = intrf.r_ports['pred'] # INT predicate read
241 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
242
243 # hack method of keeping an eye on whether branch/trap set the PC
244 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
245 self.state_nia.wen.name = 'state_nia_wen'
246
247 # pulse to synchronize the simulator at instruction end
248 self.insn_done = Signal()
249
250 if self.svp64_en:
251 # store copies of predicate masks
252 self.srcmask = Signal(64)
253 self.dstmask = Signal(64)
254
255 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
256 fetch_pc_ready_o, fetch_pc_valid_i,
257 fetch_insn_valid_o, fetch_insn_ready_i):
258 """fetch FSM
259
260 this FSM performs fetch of raw instruction data, partial-decodes
261 it 32-bit at a time to detect SVP64 prefixes, and will optionally
262 read a 2nd 32-bit quantity if that occurs.
263 """
264 comb = m.d.comb
265 sync = m.d.sync
266 pdecode2 = self.pdecode2
267 cur_state = self.cur_state
268 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
269
270 msr_read = Signal(reset=1)
271
272 with m.FSM(name='fetch_fsm'):
273
274 # waiting (zzz)
275 with m.State("IDLE"):
276 comb += fetch_pc_ready_o.eq(1)
277 with m.If(fetch_pc_valid_i):
278 # instruction allowed to go: start by reading the PC
279 # capture the PC and also drop it into Insn Memory
280 # we have joined a pair of combinatorial memory
281 # lookups together. this is Generally Bad.
282 comb += self.imem.a_pc_i.eq(pc)
283 comb += self.imem.a_valid_i.eq(1)
284 comb += self.imem.f_valid_i.eq(1)
285 sync += cur_state.pc.eq(pc)
286 sync += cur_state.svstate.eq(svstate) # and svstate
287
288 # initiate read of MSR. arrives one clock later
289 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
290 sync += msr_read.eq(0)
291
292 m.next = "INSN_READ" # move to "wait for bus" phase
293
294 # dummy pause to find out why simulation is not keeping up
295 with m.State("INSN_READ"):
296 # one cycle later, msr/sv read arrives. valid only once.
297 with m.If(~msr_read):
298 sync += msr_read.eq(1) # yeah don't read it again
299 sync += cur_state.msr.eq(self.state_r_msr.data_o)
300 with m.If(self.imem.f_busy_o): # zzz...
301 # busy: stay in wait-read
302 comb += self.imem.a_valid_i.eq(1)
303 comb += self.imem.f_valid_i.eq(1)
304 with m.Else():
305 # not busy: instruction fetched
306 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
307 if self.svp64_en:
308 svp64 = self.svp64
309 # decode the SVP64 prefix, if any
310 comb += svp64.raw_opcode_in.eq(insn)
311 comb += svp64.bigendian.eq(self.core_bigendian_i)
312 # pass the decoded prefix (if any) to PowerDecoder2
313 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
314 # remember whether this is a prefixed instruction, so
315 # the FSM can readily loop when VL==0
316 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
317 # calculate the address of the following instruction
318 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
319 sync += nia.eq(cur_state.pc + insn_size)
320 with m.If(~svp64.is_svp64_mode):
321 # with no prefix, store the instruction
322 # and hand it directly to the next FSM
323 sync += dec_opcode_i.eq(insn)
324 m.next = "INSN_READY"
325 with m.Else():
326 # fetch the rest of the instruction from memory
327 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
328 comb += self.imem.a_valid_i.eq(1)
329 comb += self.imem.f_valid_i.eq(1)
330 m.next = "INSN_READ2"
331 else:
332 # not SVP64 - 32-bit only
333 sync += nia.eq(cur_state.pc + 4)
334 sync += dec_opcode_i.eq(insn)
335 m.next = "INSN_READY"
336
337 with m.State("INSN_READ2"):
338 with m.If(self.imem.f_busy_o): # zzz...
339 # busy: stay in wait-read
340 comb += self.imem.a_valid_i.eq(1)
341 comb += self.imem.f_valid_i.eq(1)
342 with m.Else():
343 # not busy: instruction fetched
344 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
345 sync += dec_opcode_i.eq(insn)
346 m.next = "INSN_READY"
347 # TODO: probably can start looking at pdecode2.rm_dec
348 # here or maybe even in INSN_READ state, if svp64_mode
349 # detected, in order to trigger - and wait for - the
350 # predicate reading.
351 pmode = pdecode2.rm_dec.predmode
352 """
353 if pmode != SVP64PredMode.ALWAYS.value:
354 fire predicate loading FSM and wait before
355 moving to INSN_READY
356 else:
357 sync += self.srcmask.eq(-1) # set to all 1s
358 sync += self.dstmask.eq(-1) # set to all 1s
359 m.next = "INSN_READY"
360 """
361
362 with m.State("INSN_READY"):
363 # hand over the instruction, to be decoded
364 comb += fetch_insn_valid_o.eq(1)
365 with m.If(fetch_insn_ready_i):
366 m.next = "IDLE"
367
368 def fetch_predicate_fsm(self, m,
369 pred_insn_valid_i, pred_insn_ready_o,
370 pred_mask_valid_o, pred_mask_ready_i):
371 """fetch_predicate_fsm - obtains (constructs in the case of CR)
372 src/dest predicate masks
373
374 https://bugs.libre-soc.org/show_bug.cgi?id=617
375 the predicates can be read here, by using IntRegs r_ports['pred']
376 or CRRegs r_ports['pred']. in the case of CRs it will have to
377 be done through multiple reads, extracting one relevant at a time.
378 later, a faster way would be to use the 32-bit-wide CR port but
379 this is more complex decoding, here. equivalent code used in
380 ISACaller is "from soc.decoder.isa.caller import get_predcr"
381 """
382 comb = m.d.comb
383 sync = m.d.sync
384 pdecode2 = self.pdecode2
385 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
386 predmode = rm_dec.predmode
387 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
388 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
389
390 # elif predmode == CR:
391 # CR-src sidx, sinvert = get_predcr(m, srcpred)
392 # CR-dst didx, dinvert = get_predcr(m, dstpred)
393 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
394 # has to cope with first one then the other
395 # for cr_idx = FSM-state-loop(0..VL-1):
396 # FSM-state-trigger-CR-read:
397 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
398 # comb += cr_pred.ren.eq(cr_ren)
399 # FSM-state-1-clock-later-actual-Read:
400 # cr_field = Signal(4)
401 # cr_bit = Signal(1)
402 # # read the CR field, select the appropriate bit
403 # comb += cr_field.eq(cr_pred.data_o)
404 # comb += cr_bit.eq(cr_field.bit_select(idx)))
405 # # just like in branch BO tests
406 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
407
408 # decode predicates
409 sregread, sinvert, sunary = get_predint(m, srcpred, 's')
410 dregread, dinvert, dunary = get_predint(m, dstpred, 'd')
411 sidx, scrinvert = get_predcr(m, srcpred, 's')
412 didx, dcrinvert = get_predcr(m, dstpred, 'd')
413
414 with m.FSM(name="fetch_predicate"):
415
416 with m.State("FETCH_PRED_IDLE"):
417 comb += pred_insn_ready_o.eq(1)
418 with m.If(pred_insn_valid_i):
419 with m.If(predmode == SVP64PredMode.INT):
420 # fetch destination predicate register
421 comb += int_pred.addr.eq(dregread)
422 comb += int_pred.ren.eq(1)
423 m.next = "INT_DST_READ"
424 with m.Else():
425 sync += self.srcmask.eq(-1)
426 sync += self.dstmask.eq(-1)
427 m.next = "FETCH_PRED_DONE"
428
429 with m.State("INT_DST_READ"):
430 # store destination mask
431 inv = Repl(dinvert, 64)
432 sync += self.dstmask.eq(self.int_pred.data_o ^ inv)
433 # fetch source predicate register
434 comb += int_pred.addr.eq(sregread)
435 comb += int_pred.ren.eq(1)
436 m.next = "INT_SRC_READ"
437
438 with m.State("INT_SRC_READ"):
439 # store source mask
440 inv = Repl(sinvert, 64)
441 sync += self.srcmask.eq(self.int_pred.data_o ^ inv)
442 m.next = "FETCH_PRED_DONE"
443
444 with m.State("FETCH_PRED_DONE"):
445 comb += pred_mask_valid_o.eq(1)
446 with m.If(pred_mask_ready_i):
447 m.next = "FETCH_PRED_IDLE"
448
449 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
450 dbg, core_rst, is_svp64_mode,
451 fetch_pc_ready_o, fetch_pc_valid_i,
452 fetch_insn_valid_o, fetch_insn_ready_i,
453 pred_insn_valid_i, pred_insn_ready_o,
454 pred_mask_valid_o, pred_mask_ready_i,
455 exec_insn_valid_i, exec_insn_ready_o,
456 exec_pc_valid_o, exec_pc_ready_i):
457 """issue FSM
458
459 decode / issue FSM. this interacts with the "fetch" FSM
460 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
461 (outgoing). also interacts with the "execute" FSM
462 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
463 (incoming).
464 SVP64 RM prefixes have already been set up by the
465 "fetch" phase, so execute is fairly straightforward.
466 """
467
468 comb = m.d.comb
469 sync = m.d.sync
470 pdecode2 = self.pdecode2
471 cur_state = self.cur_state
472
473 # temporaries
474 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
475
476 # for updating svstate (things like srcstep etc.)
477 update_svstate = Signal() # set this (below) if updating
478 new_svstate = SVSTATERec("new_svstate")
479 comb += new_svstate.eq(cur_state.svstate)
480
481 # precalculate srcstep+1 and dststep+1
482 cur_srcstep = cur_state.svstate.srcstep
483 cur_dststep = cur_state.svstate.dststep
484 next_srcstep = Signal.like(cur_srcstep)
485 next_dststep = Signal.like(cur_dststep)
486 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
487 comb += next_dststep.eq(cur_state.svstate.dststep+1)
488
489 with m.FSM(name="issue_fsm"):
490
491 # sync with the "fetch" phase which is reading the instruction
492 # at this point, there is no instruction running, that
493 # could inadvertently update the PC.
494 with m.State("ISSUE_START"):
495 # wait on "core stop" release, before next fetch
496 # need to do this here, in case we are in a VL==0 loop
497 with m.If(~dbg.core_stop_o & ~core_rst):
498 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
499 with m.If(fetch_pc_ready_o): # fetch acknowledged us
500 m.next = "INSN_WAIT"
501 with m.Else():
502 # tell core it's stopped, and acknowledge debug handshake
503 comb += core.core_stopped_i.eq(1)
504 comb += dbg.core_stopped_i.eq(1)
505 # while stopped, allow updating the PC and SVSTATE
506 with m.If(self.pc_i.ok):
507 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
508 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
509 sync += pc_changed.eq(1)
510 with m.If(self.svstate_i.ok):
511 comb += new_svstate.eq(self.svstate_i.data)
512 comb += update_svstate.eq(1)
513 sync += sv_changed.eq(1)
514
515 # decode the instruction when it arrives
516 with m.State("INSN_WAIT"):
517 comb += fetch_insn_ready_i.eq(1)
518 with m.If(fetch_insn_valid_o):
519 # decode the instruction
520 sync += core.e.eq(pdecode2.e)
521 sync += core.state.eq(cur_state)
522 sync += core.raw_insn_i.eq(dec_opcode_i)
523 sync += core.bigendian_i.eq(self.core_bigendian_i)
524 # set RA_OR_ZERO detection in satellite decoders
525 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
526 # loop into ISSUE_START if it's a SVP64 instruction
527 # and VL == 0. this because VL==0 is a for-loop
528 # from 0 to 0 i.e. always, always a NOP.
529 cur_vl = cur_state.svstate.vl
530 with m.If(is_svp64_mode & (cur_vl == 0)):
531 # update the PC before fetching the next instruction
532 # since we are in a VL==0 loop, no instruction was
533 # executed that we could be overwriting
534 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
535 comb += self.state_w_pc.data_i.eq(nia)
536 comb += self.insn_done.eq(1)
537 m.next = "ISSUE_START"
538 with m.Else():
539 m.next = "PRED_START" # start fetching the predicate
540
541 with m.State("PRED_START"):
542 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
543 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
544 m.next = "MASK_WAIT"
545
546 with m.State("MASK_WAIT"):
547 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
548 with m.If(pred_mask_valid_o): # predication masks are ready
549 m.next = "INSN_EXECUTE"
550
551 # handshake with execution FSM, move to "wait" once acknowledged
552 with m.State("INSN_EXECUTE"):
553 # with m.If(is_svp64_mode):
554 # TODO advance src/dst step to "skip" over predicated-out
555 # from self.srcmask and self.dstmask
556 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
557 # but still without exceeding VL in either case
558 # IMPORTANT: when changing src/dest step, have to
559 # jump to m.next = "DECODE_SV" to deal with the change in
560 # SVSTATE
561
562 with m.If(is_svp64_mode):
563
564 pred_src_zero = pdecode2.rm_dec.pred_sz
565 pred_dst_zero = pdecode2.rm_dec.pred_dz
566
567 """
568 if not pred_src_zero:
569 if (((1<<cur_srcstep) & self.srcmask) == 0) and
570 (cur_srcstep != vl):
571 comb += update_svstate.eq(1)
572 comb += new_svstate.srcstep.eq(next_srcstep)
573 sync += sv_changed.eq(1)
574
575 if not pred_dst_zero:
576 if (((1<<cur_dststep) & self.dstmask) == 0) and
577 (cur_dststep != vl):
578 comb += new_svstate.dststep.eq(next_dststep)
579 comb += update_svstate.eq(1)
580 sync += sv_changed.eq(1)
581
582 if update_svstate:
583 m.next = "DECODE_SV"
584 """
585
586 comb += exec_insn_valid_i.eq(1) # trigger execute
587 with m.If(exec_insn_ready_o): # execute acknowledged us
588 m.next = "EXECUTE_WAIT"
589
590 with m.State("EXECUTE_WAIT"):
591 # wait on "core stop" release, at instruction end
592 # need to do this here, in case we are in a VL>1 loop
593 with m.If(~dbg.core_stop_o & ~core_rst):
594 comb += exec_pc_ready_i.eq(1)
595 with m.If(exec_pc_valid_o):
596
597 # was this the last loop iteration?
598 is_last = Signal()
599 cur_vl = cur_state.svstate.vl
600 comb += is_last.eq(next_srcstep == cur_vl)
601
602 # if either PC or SVSTATE were changed by the previous
603 # instruction, go directly back to Fetch, without
604 # updating either PC or SVSTATE
605 with m.If(pc_changed | sv_changed):
606 m.next = "ISSUE_START"
607
608 # also return to Fetch, when no output was a vector
609 # (regardless of SRCSTEP and VL), or when the last
610 # instruction was really the last one of the VL loop
611 with m.Elif((~pdecode2.loop_continue) | is_last):
612 # before going back to fetch, update the PC state
613 # register with the NIA.
614 # ok here we are not reading the branch unit.
615 # TODO: this just blithely overwrites whatever
616 # pipeline updated the PC
617 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
618 comb += self.state_w_pc.data_i.eq(nia)
619 # reset SRCSTEP before returning to Fetch
620 with m.If(pdecode2.loop_continue):
621 comb += new_svstate.srcstep.eq(0)
622 comb += new_svstate.dststep.eq(0)
623 comb += update_svstate.eq(1)
624 m.next = "ISSUE_START"
625
626 # returning to Execute? then, first update SRCSTEP
627 with m.Else():
628 comb += new_svstate.srcstep.eq(next_srcstep)
629 comb += new_svstate.dststep.eq(next_dststep)
630 comb += update_svstate.eq(1)
631 m.next = "DECODE_SV"
632
633 with m.Else():
634 comb += core.core_stopped_i.eq(1)
635 comb += dbg.core_stopped_i.eq(1)
636 # while stopped, allow updating the PC and SVSTATE
637 with m.If(self.pc_i.ok):
638 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
639 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
640 sync += pc_changed.eq(1)
641 with m.If(self.svstate_i.ok):
642 comb += new_svstate.eq(self.svstate_i.data)
643 comb += update_svstate.eq(1)
644 sync += sv_changed.eq(1)
645
646 # need to decode the instruction again, after updating SRCSTEP
647 # in the previous state.
648 # mostly a copy of INSN_WAIT, but without the actual wait
649 with m.State("DECODE_SV"):
650 # decode the instruction
651 sync += core.e.eq(pdecode2.e)
652 sync += core.state.eq(cur_state)
653 sync += core.bigendian_i.eq(self.core_bigendian_i)
654 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
655 m.next = "INSN_EXECUTE" # move to "execute"
656
657 # check if svstate needs updating: if so, write it to State Regfile
658 with m.If(update_svstate):
659 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
660 comb += self.state_w_sv.data_i.eq(new_svstate)
661 sync += cur_state.svstate.eq(new_svstate) # for next clock
662
663 def execute_fsm(self, m, core, pc_changed, sv_changed,
664 exec_insn_valid_i, exec_insn_ready_o,
665 exec_pc_valid_o, exec_pc_ready_i):
666 """execute FSM
667
668 execute FSM. this interacts with the "issue" FSM
669 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
670 (outgoing). SVP64 RM prefixes have already been set up by the
671 "issue" phase, so execute is fairly straightforward.
672 """
673
674 comb = m.d.comb
675 sync = m.d.sync
676 pdecode2 = self.pdecode2
677
678 # temporaries
679 core_busy_o = core.busy_o # core is busy
680 core_ivalid_i = core.ivalid_i # instruction is valid
681 core_issue_i = core.issue_i # instruction is issued
682 insn_type = core.e.do.insn_type # instruction MicroOp type
683
684 with m.FSM(name="exec_fsm"):
685
686 # waiting for instruction bus (stays there until not busy)
687 with m.State("INSN_START"):
688 comb += exec_insn_ready_o.eq(1)
689 with m.If(exec_insn_valid_i):
690 comb += core_ivalid_i.eq(1) # instruction is valid
691 comb += core_issue_i.eq(1) # and issued
692 sync += sv_changed.eq(0)
693 sync += pc_changed.eq(0)
694 m.next = "INSN_ACTIVE" # move to "wait completion"
695
696 # instruction started: must wait till it finishes
697 with m.State("INSN_ACTIVE"):
698 with m.If(insn_type != MicrOp.OP_NOP):
699 comb += core_ivalid_i.eq(1) # instruction is valid
700 # note changes to PC and SVSTATE
701 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
702 sync += sv_changed.eq(1)
703 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
704 sync += pc_changed.eq(1)
705 with m.If(~core_busy_o): # instruction done!
706 comb += exec_pc_valid_o.eq(1)
707 with m.If(exec_pc_ready_i):
708 comb += self.insn_done.eq(1)
709 m.next = "INSN_START" # back to fetch
710
711 def setup_peripherals(self, m):
712 comb, sync = m.d.comb, m.d.sync
713
714 m.submodules.core = core = DomainRenamer("coresync")(self.core)
715 m.submodules.imem = imem = self.imem
716 m.submodules.dbg = dbg = self.dbg
717 if self.jtag_en:
718 m.submodules.jtag = jtag = self.jtag
719 # TODO: UART2GDB mux, here, from external pin
720 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
721 sync += dbg.dmi.connect_to(jtag.dmi)
722
723 cur_state = self.cur_state
724
725 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
726 if self.sram4x4k:
727 for i, sram in enumerate(self.sram4k):
728 m.submodules["sram4k_%d" % i] = sram
729 comb += sram.enable.eq(self.wb_sram_en)
730
731 # XICS interrupt handler
732 if self.xics:
733 m.submodules.xics_icp = icp = self.xics_icp
734 m.submodules.xics_ics = ics = self.xics_ics
735 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
736 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
737
738 # GPIO test peripheral
739 if self.gpio:
740 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
741
742 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
743 # XXX causes litex ECP5 test to get wrong idea about input and output
744 # (but works with verilator sim *sigh*)
745 #if self.gpio and self.xics:
746 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
747
748 # instruction decoder
749 pdecode = create_pdecode()
750 m.submodules.dec2 = pdecode2 = self.pdecode2
751 if self.svp64_en:
752 m.submodules.svp64 = svp64 = self.svp64
753
754 # convenience
755 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
756 intrf = self.core.regs.rf['int']
757
758 # clock delay power-on reset
759 cd_por = ClockDomain(reset_less=True)
760 cd_sync = ClockDomain()
761 core_sync = ClockDomain("coresync")
762 m.domains += cd_por, cd_sync, core_sync
763
764 ti_rst = Signal(reset_less=True)
765 delay = Signal(range(4), reset=3)
766 with m.If(delay != 0):
767 m.d.por += delay.eq(delay - 1)
768 comb += cd_por.clk.eq(ClockSignal())
769
770 # power-on reset delay
771 core_rst = ResetSignal("coresync")
772 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
773 comb += core_rst.eq(ti_rst)
774
775 # busy/halted signals from core
776 comb += self.busy_o.eq(core.busy_o)
777 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
778
779 # temporary hack: says "go" immediately for both address gen and ST
780 l0 = core.l0
781 ldst = core.fus.fus['ldst0']
782 st_go_edge = rising_edge(m, ldst.st.rel_o)
783 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
784 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
785
786 return core_rst
787
788 def elaborate(self, platform):
789 m = Module()
790 # convenience
791 comb, sync = m.d.comb, m.d.sync
792 cur_state = self.cur_state
793 pdecode2 = self.pdecode2
794 dbg = self.dbg
795 core = self.core
796
797 # set up peripherals and core
798 core_rst = self.setup_peripherals(m)
799
800 # PC and instruction from I-Memory
801 comb += self.pc_o.eq(cur_state.pc)
802 pc_changed = Signal() # note write to PC
803 sv_changed = Signal() # note write to SVSTATE
804
805 # read state either from incoming override or from regfile
806 # TODO: really should be doing MSR in the same way
807 pc = state_get(m, self.pc_i, "pc", # read PC
808 self.state_r_pc, StateRegs.PC)
809 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
810 self.state_r_sv, StateRegs.SVSTATE)
811
812 # don't write pc every cycle
813 comb += self.state_w_pc.wen.eq(0)
814 comb += self.state_w_pc.data_i.eq(0)
815
816 # don't read msr every cycle
817 comb += self.state_r_msr.ren.eq(0)
818
819 # address of the next instruction, in the absence of a branch
820 # depends on the instruction size
821 nia = Signal(64, reset_less=True)
822
823 # connect up debug signals
824 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
825 comb += dbg.terminate_i.eq(core.core_terminate_o)
826 comb += dbg.state.pc.eq(pc)
827 comb += dbg.state.svstate.eq(svstate)
828 comb += dbg.state.msr.eq(cur_state.msr)
829
830 # pass the prefix mode from Fetch to Issue, so the latter can loop
831 # on VL==0
832 is_svp64_mode = Signal()
833
834 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
835 # these are the handshake signals between fetch and decode/execute
836
837 # fetch FSM can run as soon as the PC is valid
838 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
839 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
840
841 # fetch FSM hands over the instruction to be decoded / issued
842 fetch_insn_valid_o = Signal()
843 fetch_insn_ready_i = Signal()
844
845 # predicate fetch FSM decodes and fetches the predicate
846 pred_insn_valid_i = Signal()
847 pred_insn_ready_o = Signal()
848
849 # predicate fetch FSM delivers the masks
850 pred_mask_valid_o = Signal()
851 pred_mask_ready_i = Signal()
852
853 # issue FSM delivers the instruction to the be executed
854 exec_insn_valid_i = Signal()
855 exec_insn_ready_o = Signal()
856
857 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
858 exec_pc_valid_o = Signal()
859 exec_pc_ready_i = Signal()
860
861 # the FSMs here are perhaps unusual in that they detect conditions
862 # then "hold" information, combinatorially, for the core
863 # (as opposed to using sync - which would be on a clock's delay)
864 # this includes the actual opcode, valid flags and so on.
865
866 # Fetch, then predicate fetch, then Issue, then Execute.
867 # Issue is where the VL for-loop # lives. the ready/valid
868 # signalling is used to communicate between the four.
869
870 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
871 fetch_pc_ready_o, fetch_pc_valid_i,
872 fetch_insn_valid_o, fetch_insn_ready_i)
873
874 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
875 dbg, core_rst, is_svp64_mode,
876 fetch_pc_ready_o, fetch_pc_valid_i,
877 fetch_insn_valid_o, fetch_insn_ready_i,
878 pred_insn_valid_i, pred_insn_ready_o,
879 pred_mask_valid_o, pred_mask_ready_i,
880 exec_insn_valid_i, exec_insn_ready_o,
881 exec_pc_valid_o, exec_pc_ready_i)
882
883 self.fetch_predicate_fsm(m,
884 pred_insn_valid_i, pred_insn_ready_o,
885 pred_mask_valid_o, pred_mask_ready_i)
886
887 self.execute_fsm(m, core, pc_changed, sv_changed,
888 exec_insn_valid_i, exec_insn_ready_o,
889 exec_pc_valid_o, exec_pc_ready_i)
890
891 # this bit doesn't have to be in the FSM: connect up to read
892 # regfiles on demand from DMI
893 self.do_dmi(m, dbg)
894
895 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
896 # (which uses that in PowerDecoder2 to raise 0x900 exception)
897 self.tb_dec_fsm(m, cur_state.dec)
898
899 return m
900
901 def do_dmi(self, m, dbg):
902 """deals with DMI debug requests
903
904 currently only provides read requests for the INT regfile, CR and XER
905 it will later also deal with *writing* to these regfiles.
906 """
907 comb = m.d.comb
908 sync = m.d.sync
909 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
910 intrf = self.core.regs.rf['int']
911
912 with m.If(d_reg.req): # request for regfile access being made
913 # TODO: error-check this
914 # XXX should this be combinatorial? sync better?
915 if intrf.unary:
916 comb += self.int_r.ren.eq(1<<d_reg.addr)
917 else:
918 comb += self.int_r.addr.eq(d_reg.addr)
919 comb += self.int_r.ren.eq(1)
920 d_reg_delay = Signal()
921 sync += d_reg_delay.eq(d_reg.req)
922 with m.If(d_reg_delay):
923 # data arrives one clock later
924 comb += d_reg.data.eq(self.int_r.data_o)
925 comb += d_reg.ack.eq(1)
926
927 # sigh same thing for CR debug
928 with m.If(d_cr.req): # request for regfile access being made
929 comb += self.cr_r.ren.eq(0b11111111) # enable all
930 d_cr_delay = Signal()
931 sync += d_cr_delay.eq(d_cr.req)
932 with m.If(d_cr_delay):
933 # data arrives one clock later
934 comb += d_cr.data.eq(self.cr_r.data_o)
935 comb += d_cr.ack.eq(1)
936
937 # aaand XER...
938 with m.If(d_xer.req): # request for regfile access being made
939 comb += self.xer_r.ren.eq(0b111111) # enable all
940 d_xer_delay = Signal()
941 sync += d_xer_delay.eq(d_xer.req)
942 with m.If(d_xer_delay):
943 # data arrives one clock later
944 comb += d_xer.data.eq(self.xer_r.data_o)
945 comb += d_xer.ack.eq(1)
946
947 def tb_dec_fsm(self, m, spr_dec):
948 """tb_dec_fsm
949
950 this is a FSM for updating either dec or tb. it runs alternately
951 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
952 value to DEC, however the regfile has "passthrough" on it so this
953 *should* be ok.
954
955 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
956 """
957
958 comb, sync = m.d.comb, m.d.sync
959 fast_rf = self.core.regs.rf['fast']
960 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
961 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
962
963 with m.FSM() as fsm:
964
965 # initiates read of current DEC
966 with m.State("DEC_READ"):
967 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
968 comb += fast_r_dectb.ren.eq(1)
969 m.next = "DEC_WRITE"
970
971 # waits for DEC read to arrive (1 cycle), updates with new value
972 with m.State("DEC_WRITE"):
973 new_dec = Signal(64)
974 # TODO: MSR.LPCR 32-bit decrement mode
975 comb += new_dec.eq(fast_r_dectb.data_o - 1)
976 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
977 comb += fast_w_dectb.wen.eq(1)
978 comb += fast_w_dectb.data_i.eq(new_dec)
979 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
980 m.next = "TB_READ"
981
982 # initiates read of current TB
983 with m.State("TB_READ"):
984 comb += fast_r_dectb.addr.eq(FastRegs.TB)
985 comb += fast_r_dectb.ren.eq(1)
986 m.next = "TB_WRITE"
987
988 # waits for read TB to arrive, initiates write of current TB
989 with m.State("TB_WRITE"):
990 new_tb = Signal(64)
991 comb += new_tb.eq(fast_r_dectb.data_o + 1)
992 comb += fast_w_dectb.addr.eq(FastRegs.TB)
993 comb += fast_w_dectb.wen.eq(1)
994 comb += fast_w_dectb.data_i.eq(new_tb)
995 m.next = "DEC_READ"
996
997 return m
998
999 def __iter__(self):
1000 yield from self.pc_i.ports()
1001 yield self.pc_o
1002 yield self.memerr_o
1003 yield from self.core.ports()
1004 yield from self.imem.ports()
1005 yield self.core_bigendian_i
1006 yield self.busy_o
1007
1008 def ports(self):
1009 return list(self)
1010
1011 def external_ports(self):
1012 ports = self.pc_i.ports()
1013 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1014 ]
1015
1016 if self.jtag_en:
1017 ports += list(self.jtag.external_ports())
1018 else:
1019 # don't add DMI if JTAG is enabled
1020 ports += list(self.dbg.dmi.ports())
1021
1022 ports += list(self.imem.ibus.fields.values())
1023 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1024
1025 if self.sram4x4k:
1026 for sram in self.sram4k:
1027 ports += list(sram.bus.fields.values())
1028
1029 if self.xics:
1030 ports += list(self.xics_icp.bus.fields.values())
1031 ports += list(self.xics_ics.bus.fields.values())
1032 ports.append(self.int_level_i)
1033
1034 if self.gpio:
1035 ports += list(self.simple_gpio.bus.fields.values())
1036 ports.append(self.gpio_o)
1037
1038 return ports
1039
1040 def ports(self):
1041 return list(self)
1042
1043
1044 class TestIssuer(Elaboratable):
1045 def __init__(self, pspec):
1046 self.ti = TestIssuerInternal(pspec)
1047
1048 self.pll = DummyPLL()
1049
1050 # PLL direct clock or not
1051 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1052 if self.pll_en:
1053 self.pll_18_o = Signal(reset_less=True)
1054
1055 def elaborate(self, platform):
1056 m = Module()
1057 comb = m.d.comb
1058
1059 # TestIssuer runs at direct clock
1060 m.submodules.ti = ti = self.ti
1061 cd_int = ClockDomain("coresync")
1062
1063 if self.pll_en:
1064 # ClockSelect runs at PLL output internal clock rate
1065 m.submodules.pll = pll = self.pll
1066
1067 # add clock domains from PLL
1068 cd_pll = ClockDomain("pllclk")
1069 m.domains += cd_pll
1070
1071 # PLL clock established. has the side-effect of running clklsel
1072 # at the PLL's speed (see DomainRenamer("pllclk") above)
1073 pllclk = ClockSignal("pllclk")
1074 comb += pllclk.eq(pll.clk_pll_o)
1075
1076 # wire up external 24mhz to PLL
1077 comb += pll.clk_24_i.eq(ClockSignal())
1078
1079 # output 18 mhz PLL test signal
1080 comb += self.pll_18_o.eq(pll.pll_18_o)
1081
1082 # now wire up ResetSignals. don't mind them being in this domain
1083 pll_rst = ResetSignal("pllclk")
1084 comb += pll_rst.eq(ResetSignal())
1085
1086 # internal clock is set to selector clock-out. has the side-effect of
1087 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1088 intclk = ClockSignal("coresync")
1089 if self.pll_en:
1090 comb += intclk.eq(pll.clk_pll_o)
1091 else:
1092 comb += intclk.eq(ClockSignal())
1093
1094 return m
1095
1096 def ports(self):
1097 return list(self.ti.ports()) + list(self.pll.ports()) + \
1098 [ClockSignal(), ResetSignal()]
1099
1100 def external_ports(self):
1101 ports = self.ti.external_ports()
1102 ports.append(ClockSignal())
1103 ports.append(ResetSignal())
1104 if self.pll_en:
1105 ports.append(self.pll.clk_sel_i)
1106 ports.append(self.pll_18_o)
1107 ports.append(self.pll.pll_lck_o)
1108 return ports
1109
1110
1111 if __name__ == '__main__':
1112 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1113 'spr': 1,
1114 'div': 1,
1115 'mul': 1,
1116 'shiftrot': 1
1117 }
1118 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1119 imem_ifacetype='bare_wb',
1120 addr_wid=48,
1121 mask_wid=8,
1122 reg_wid=64,
1123 units=units)
1124 dut = TestIssuer(pspec)
1125 vl = main(dut, ports=dut.ports(), name="test_issuer")
1126
1127 if len(sys.argv) == 1:
1128 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1129 with open("test_issuer.il", "w") as f:
1130 f.write(vl)