src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  89                                                     features={'err'}))
  90
  91         # add interrupt controller?
  92         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  93         if self.xics:
  94             self.xics_icp = XICS_ICP()
  95             self.xics_ics = XICS_ICS()
  96             self.int_level_i = self.xics_ics.int_level_i
  97
  98         # add GPIO peripheral?
  99         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 100         if self.gpio:
 101             self.simple_gpio = SimpleGPIO()
 102             self.gpio_o = self.simple_gpio.gpio_o
 103
 104         # main instruction core25
 105         self.core = core = NonProductionCore(pspec)
 106
 107         # instruction decoder.  goes into Trap Record
 108         pdecode = create_pdecode()
 109         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 110         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 111                                      opkls=IssuerDecode2ToOperand)
 112         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 113
 114         # Test Instruction memory
 115         self.imem = ConfigFetchUnit(pspec).fu
 116         # one-row cache of instruction read
 117         self.iline = Signal(64) # one instruction line
 118         self.iprev_adr = Signal(64) # previous address: if different, do read
 119
 120         # DMI interface
 121         self.dbg = CoreDebug()
 122
 123         # instruction go/monitor
 124         self.pc_o = Signal(64, reset_less=True)
 125         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 126         self.svstate_i = Data(32, "svstate_i") # ditto
 127         self.core_bigendian_i = Signal()
 128         self.busy_o = Signal(reset_less=True)
 129         self.memerr_o = Signal(reset_less=True)
 130
 131         # STATE regfile read /write ports for PC, MSR, SVSTATE
 132         staterf = self.core.regs.rf['state']
 133         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 134         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 135         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 136         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 137         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 138
 139         # DMI interface access
 140         intrf = self.core.regs.rf['int']
 141         crrf = self.core.regs.rf['cr']
 142         xerrf = self.core.regs.rf['xer']
 143         self.int_r = intrf.r_ports['dmi'] # INT read
 144         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 145         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 146
 147         # hack method of keeping an eye on whether branch/trap set the PC
 148         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 149         self.state_nia.wen.name = 'state_nia_wen'
 150
 151     def fetch_fsm(self, m, core, pc, svstate, nia,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164
 165         # latches copy of raw fetched instruction
 166         fetch_insn_o = Signal(32, reset_less=True)
 167         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 168         sync += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 169
 170         msr_read = Signal(reset=1)
 171
 172         with m.FSM(name='fetch_fsm'):
 173
 174             # waiting (zzz)
 175             with m.State("IDLE"):
 176                 comb += fetch_pc_ready_o.eq(1)
 177                 with m.If(fetch_pc_valid_i):
 178                     # instruction allowed to go: start by reading the PC
 179                     # capture the PC and also drop it into Insn Memory
 180                     # we have joined a pair of combinatorial memory
 181                     # lookups together.  this is Generally Bad.
 182                     comb += self.imem.a_pc_i.eq(pc)
 183                     comb += self.imem.a_valid_i.eq(1)
 184                     comb += self.imem.f_valid_i.eq(1)
 185                     sync += cur_state.pc.eq(pc)
 186                     sync += cur_state.svstate.eq(svstate) # and svstate
 187
 188                     # initiate read of MSR. arrives one clock later
 189                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 190                     sync += msr_read.eq(0)
 191
 192                     m.next = "INSN_READ"  # move to "wait for bus" phase
 193
 194             # dummy pause to find out why simulation is not keeping up
 195             with m.State("INSN_READ"):
 196                 # one cycle later, msr/sv read arrives.  valid only once.
 197                 with m.If(~msr_read):
 198                     sync += msr_read.eq(1) # yeah don't read it again
 199                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 200                 with m.If(self.imem.f_busy_o): # zzz...
 201                     # busy: stay in wait-read
 202                     comb += self.imem.a_valid_i.eq(1)
 203                     comb += self.imem.f_valid_i.eq(1)
 204                 with m.Else():
 205                     # not busy: instruction fetched
 206                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 207                     # decode the SVP64 prefix, if any
 208                     comb += svp64.raw_opcode_in.eq(insn)
 209                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 210                     # pass the decoded prefix (if any) to PowerDecoder2
 211                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 212                     # calculate the address of the following instruction
 213                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 214                     sync += nia.eq(cur_state.pc + insn_size)
 215                     with m.If(~svp64.is_svp64_mode):
 216                         # with no prefix, store the instruction
 217                         # and hand it directly to the next FSM
 218                         comb += fetch_insn_o.eq(insn)
 219                         m.next = "INSN_READY"
 220                     with m.Else():
 221                         # fetch the rest of the instruction from memory
 222                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 223                         comb += self.imem.a_valid_i.eq(1)
 224                         comb += self.imem.f_valid_i.eq(1)
 225                         m.next = "INSN_READ2"
 226
 227             with m.State("INSN_READ2"):
 228                 with m.If(self.imem.f_busy_o):  # zzz...
 229                     # busy: stay in wait-read
 230                     comb += self.imem.a_valid_i.eq(1)
 231                     comb += self.imem.f_valid_i.eq(1)
 232                 with m.Else():
 233                     # not busy: instruction fetched
 234                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 235                     comb += fetch_insn_o.eq(insn)
 236                     m.next = "INSN_READY"
 237
 238             with m.State("INSN_READY"):
 239                 # hand over the instruction, to be decoded
 240                 comb += fetch_insn_valid_o.eq(1)
 241                 with m.If(fetch_insn_ready_i):
 242                     m.next = "IDLE"
 243
 244     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 245                   dbg, core_rst,
 246                   fetch_pc_ready_o, fetch_pc_valid_i,
 247                   fetch_insn_valid_o, fetch_insn_ready_i,
 248                   exec_insn_valid_i, exec_insn_ready_o,
 249                   exec_pc_valid_o, exec_pc_ready_i):
 250         """issue FSM
 251
 252         decode / issue FSM.  this interacts with the "fetch" FSM
 253         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 254         (outgoing). also interacts with the "execute" FSM
 255         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 256         (incoming).
 257         SVP64 RM prefixes have already been set up by the
 258         "fetch" phase, so execute is fairly straightforward.
 259         """
 260
 261         comb = m.d.comb
 262         sync = m.d.sync
 263         pdecode2 = self.pdecode2
 264         cur_state = self.cur_state
 265
 266         # temporaries
 267         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 268
 269         # for updating svstate (things like srcstep etc.)
 270         update_svstate = Signal() # set this (below) if updating
 271         new_svstate = SVSTATERec("new_svstate")
 272         comb += new_svstate.eq(cur_state.svstate)
 273
 274         with m.FSM(name="issue_fsm"):
 275
 276             # Wait on "core stop" release, at reset
 277             with m.State("WAIT_RESET"):
 278                 with m.If(~dbg.core_stop_o & ~core_rst):
 279                     m.next = "INSN_FETCH"
 280                 with m.Else():
 281                     comb += core.core_stopped_i.eq(1)
 282                     comb += dbg.core_stopped_i.eq(1)
 283
 284             # go fetch the instruction at the current PC
 285             # at this point, there is no instruction running, that
 286             # could inadvertently update the PC.
 287             with m.State("INSN_FETCH"):
 288                 # TODO: update PC here, before fetch
 289                 comb += fetch_pc_valid_i.eq(1)
 290                 with m.If(fetch_pc_ready_o):
 291                     m.next = "INSN_WAIT"
 292
 293             # decode the instruction when it arrives
 294             with m.State("INSN_WAIT"):
 295                 comb += fetch_insn_ready_i.eq(1)
 296                 with m.If(fetch_insn_valid_o):
 297                     # decode the instruction
 298                     sync += core.e.eq(pdecode2.e)
 299                     sync += core.state.eq(cur_state)
 300                     sync += core.raw_insn_i.eq(dec_opcode_i)
 301                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 302                     # TODO: loop into INSN_FETCH if it's a vector instruction
 303                     #       and VL == 0.  this because VL==0 is a for-loop
 304                     #       from 0 to 0 i.e. always, always a NOP.
 305                     m.next = "INSN_EXECUTE"  # move to "execute"
 306
 307             with m.State("INSN_EXECUTE"):
 308                 comb += exec_insn_valid_i.eq(1)
 309                 with m.If(exec_insn_ready_o):
 310                     m.next = "EXECUTE_WAIT"
 311
 312             with m.State("EXECUTE_WAIT"):
 313                 # wait on "core stop" release, at instruction end
 314                 with m.If(~dbg.core_stop_o & ~core_rst):
 315                     comb += exec_pc_ready_i.eq(1)
 316                     with m.If(exec_pc_valid_o):
 317                         # TODO: update SRCSTEP here (in new_svstate)
 318                         #       and set update_svstate to True *as long as*
 319                         #       PC / SVSTATE was not modified.  that's an
 320                         #       exception (or setvl was called)
 321                         # TODO: loop into INSN_EXECUTE if it's a vector
 322                         #       instruction and SRCSTEP != VL-1 and
 323                         #       PowerDecoder.no_out_vec is True
 324                         #       unless PC / SVSTATE was modified, in that
 325                         #       case do go back to INSN_FETCH.
 326
 327                         # before fetch, update the PC state register with
 328                         # the NIA, unless PC was modified in execute
 329                         with m.If(~pc_changed):
 330                             # ok here we are not reading the branch unit.
 331                             # TODO: this just blithely overwrites whatever
 332                             #       pipeline updated the PC
 333                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 334                             comb += self.state_w_pc.data_i.eq(nia)
 335                         m.next = "INSN_FETCH"
 336                 with m.Else():
 337                     comb += core.core_stopped_i.eq(1)
 338                     comb += dbg.core_stopped_i.eq(1)
 339
 340         # check if svstate needs updating: if so, write it to State Regfile
 341         with m.If(update_svstate):
 342             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 343             comb += self.state_w_sv.data_i.eq(new_svstate)
 344             sync += cur_state.svstate.eq(new_svstate) # for next clock
 345
 346     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 347                     exec_insn_valid_i, exec_insn_ready_o,
 348                     exec_pc_valid_o, exec_pc_ready_i):
 349         """execute FSM
 350
 351         execute FSM. this interacts with the "issue" FSM
 352         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 353         (outgoing). SVP64 RM prefixes have already been set up by the
 354         "issue" phase, so execute is fairly straightforward.
 355         """
 356
 357         comb = m.d.comb
 358         sync = m.d.sync
 359         pdecode2 = self.pdecode2
 360         svp64 = self.svp64
 361
 362         # temporaries
 363         core_busy_o = core.busy_o                 # core is busy
 364         core_ivalid_i = core.ivalid_i             # instruction is valid
 365         core_issue_i = core.issue_i               # instruction is issued
 366         insn_type = core.e.do.insn_type           # instruction MicroOp type
 367
 368         with m.FSM(name="exec_fsm"):
 369
 370             # waiting for instruction bus (stays there until not busy)
 371             with m.State("INSN_START"):
 372                 comb += exec_insn_ready_o.eq(1)
 373                 with m.If(exec_insn_valid_i):
 374                     comb += core_ivalid_i.eq(1)  # instruction is valid
 375                     comb += core_issue_i.eq(1)  # and issued
 376                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 377
 378             # instruction started: must wait till it finishes
 379             with m.State("INSN_ACTIVE"):
 380                 with m.If(insn_type != MicrOp.OP_NOP):
 381                     comb += core_ivalid_i.eq(1) # instruction is valid
 382                 # note changes to PC and SVSTATE
 383                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 384                     sync += sv_changed.eq(1)
 385                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 386                     sync += pc_changed.eq(1)
 387                 with m.If(~core_busy_o): # instruction done!
 388                     comb += insn_done.eq(1)
 389                     sync += core.e.eq(0)
 390                     sync += core.raw_insn_i.eq(0)
 391                     sync += core.bigendian_i.eq(0)
 392                     sync += sv_changed.eq(0)
 393                     sync += pc_changed.eq(0)
 394                     comb += exec_pc_valid_o.eq(1)
 395                     with m.If(exec_pc_ready_i):
 396                         m.next = "INSN_START"  # back to fetch
 397
 398     def elaborate(self, platform):
 399         m = Module()
 400         comb, sync = m.d.comb, m.d.sync
 401
 402         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 403         m.submodules.imem = imem = self.imem
 404         m.submodules.dbg = dbg = self.dbg
 405         if self.jtag_en:
 406             m.submodules.jtag = jtag = self.jtag
 407             # TODO: UART2GDB mux, here, from external pin
 408             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 409             sync += dbg.dmi.connect_to(jtag.dmi)
 410
 411         cur_state = self.cur_state
 412
 413         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 414         if self.sram4x4k:
 415             for i, sram in enumerate(self.sram4k):
 416                 m.submodules["sram4k_%d" % i] = sram
 417                 comb += sram.enable.eq(self.wb_sram_en)
 418
 419         # XICS interrupt handler
 420         if self.xics:
 421             m.submodules.xics_icp = icp = self.xics_icp
 422             m.submodules.xics_ics = ics = self.xics_ics
 423             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 424             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 425
 426         # GPIO test peripheral
 427         if self.gpio:
 428             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 429
 430         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 431         # XXX causes litex ECP5 test to get wrong idea about input and output
 432         # (but works with verilator sim *sigh*)
 433         #if self.gpio and self.xics:
 434         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 435
 436         # instruction decoder
 437         pdecode = create_pdecode()
 438         m.submodules.dec2 = pdecode2 = self.pdecode2
 439         m.submodules.svp64 = svp64 = self.svp64
 440
 441         # convenience
 442         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 443         intrf = self.core.regs.rf['int']
 444
 445         # clock delay power-on reset
 446         cd_por  = ClockDomain(reset_less=True)
 447         cd_sync = ClockDomain()
 448         core_sync = ClockDomain("coresync")
 449         m.domains += cd_por, cd_sync, core_sync
 450
 451         ti_rst = Signal(reset_less=True)
 452         delay = Signal(range(4), reset=3)
 453         with m.If(delay != 0):
 454             m.d.por += delay.eq(delay - 1)
 455         comb += cd_por.clk.eq(ClockSignal())
 456
 457         # power-on reset delay
 458         core_rst = ResetSignal("coresync")
 459         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 460         comb += core_rst.eq(ti_rst)
 461
 462         # busy/halted signals from core
 463         comb += self.busy_o.eq(core.busy_o)
 464         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 465
 466         # temporary hack: says "go" immediately for both address gen and ST
 467         l0 = core.l0
 468         ldst = core.fus.fus['ldst0']
 469         st_go_edge = rising_edge(m, ldst.st.rel_o)
 470         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 471         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 472
 473         # PC and instruction from I-Memory
 474         comb += self.pc_o.eq(cur_state.pc)
 475         pc_changed = Signal() # note write to PC
 476         sv_changed = Signal() # note write to SVSTATE
 477         insn_done = Signal()  # fires just once
 478
 479         # read the PC
 480         pc = Signal(64, reset_less=True)
 481         pc_ok_delay = Signal()
 482         sync += pc_ok_delay.eq(~self.pc_i.ok)
 483         with m.If(self.pc_i.ok):
 484             # incoming override (start from pc_i)
 485             comb += pc.eq(self.pc_i.data)
 486         with m.Else():
 487             # otherwise read StateRegs regfile for PC...
 488             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 489         # ... but on a 1-clock delay
 490         with m.If(pc_ok_delay):
 491             comb += pc.eq(self.state_r_pc.data_o)
 492
 493         # read svstate
 494         svstate = Signal(64, reset_less=True)
 495         svstate_ok_delay = Signal()
 496         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 497         with m.If(self.svstate_i.ok):
 498             # incoming override (start from svstate__i)
 499             comb += svstate.eq(self.svstate_i.data)
 500         with m.Else():
 501             # otherwise read StateRegs regfile for SVSTATE...
 502             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 503         # ... but on a 1-clock delay
 504         with m.If(svstate_ok_delay):
 505             comb += svstate.eq(self.state_r_sv.data_o)
 506
 507         # don't write pc every cycle
 508         comb += self.state_w_pc.wen.eq(0)
 509         comb += self.state_w_pc.data_i.eq(0)
 510
 511         # don't read msr every cycle
 512         comb += self.state_r_msr.ren.eq(0)
 513
 514         # address of the next instruction, in the absence of a branch
 515         # depends on the instruction size
 516         nia = Signal(64, reset_less=True)
 517
 518         # connect up debug signals
 519         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 520         comb += dbg.terminate_i.eq(core.core_terminate_o)
 521         comb += dbg.state.pc.eq(pc)
 522         comb += dbg.state.svstate.eq(svstate)
 523         comb += dbg.state.msr.eq(cur_state.msr)
 524
 525         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 526         # these are the handshake signals between fetch and decode/execute
 527
 528         # fetch FSM can run as soon as the PC is valid
 529         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 530         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 531
 532         # fetch FSM hands over the instruction to be decoded / issued
 533         fetch_insn_valid_o = Signal()
 534         fetch_insn_ready_i = Signal()
 535
 536         # issue FSM delivers the instruction to the be executed
 537         exec_insn_valid_i = Signal()
 538         exec_insn_ready_o = Signal()
 539
 540         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 541         exec_pc_valid_o = Signal()
 542         exec_pc_ready_i = Signal()
 543
 544         # actually use a nmigen FSM for the first time (w00t)
 545         # this FSM is perhaps unusual in that it detects conditions
 546         # then "holds" information, combinatorially, for the core
 547         # (as opposed to using sync - which would be on a clock's delay)
 548         # this includes the actual opcode, valid flags and so on.
 549
 550         self.fetch_fsm(m, core, pc, svstate, nia,
 551                        fetch_pc_ready_o, fetch_pc_valid_i,
 552                        fetch_insn_valid_o, fetch_insn_ready_i)
 553
 554         # TODO: an SVSTATE-based for-loop FSM that goes in between
 555         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 556         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 557         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 558                        dbg, core_rst,
 559                        fetch_pc_ready_o, fetch_pc_valid_i,
 560                        fetch_insn_valid_o, fetch_insn_ready_i,
 561                        exec_insn_valid_i, exec_insn_ready_o,
 562                        exec_pc_ready_i, exec_pc_valid_o)
 563
 564         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 565                          exec_insn_valid_i, exec_insn_ready_o,
 566                          exec_pc_ready_i, exec_pc_valid_o)
 567
 568         # this bit doesn't have to be in the FSM: connect up to read
 569         # regfiles on demand from DMI
 570         with m.If(d_reg.req): # request for regfile access being made
 571             # TODO: error-check this
 572             # XXX should this be combinatorial?  sync better?
 573             if intrf.unary:
 574                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 575             else:
 576                 comb += self.int_r.addr.eq(d_reg.addr)
 577                 comb += self.int_r.ren.eq(1)
 578         d_reg_delay  = Signal()
 579         sync += d_reg_delay.eq(d_reg.req)
 580         with m.If(d_reg_delay):
 581             # data arrives one clock later
 582             comb += d_reg.data.eq(self.int_r.data_o)
 583             comb += d_reg.ack.eq(1)
 584
 585         # sigh same thing for CR debug
 586         with m.If(d_cr.req): # request for regfile access being made
 587             comb += self.cr_r.ren.eq(0b11111111) # enable all
 588         d_cr_delay  = Signal()
 589         sync += d_cr_delay.eq(d_cr.req)
 590         with m.If(d_cr_delay):
 591             # data arrives one clock later
 592             comb += d_cr.data.eq(self.cr_r.data_o)
 593             comb += d_cr.ack.eq(1)
 594
 595         # aaand XER...
 596         with m.If(d_xer.req): # request for regfile access being made
 597             comb += self.xer_r.ren.eq(0b111111) # enable all
 598         d_xer_delay  = Signal()
 599         sync += d_xer_delay.eq(d_xer.req)
 600         with m.If(d_xer_delay):
 601             # data arrives one clock later
 602             comb += d_xer.data.eq(self.xer_r.data_o)
 603             comb += d_xer.ack.eq(1)
 604
 605         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 606         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 607         self.tb_dec_fsm(m, cur_state.dec)
 608
 609         return m
 610
 611     def tb_dec_fsm(self, m, spr_dec):
 612         """tb_dec_fsm
 613
 614         this is a FSM for updating either dec or tb.  it runs alternately
 615         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 616         value to DEC, however the regfile has "passthrough" on it so this
 617         *should* be ok.
 618
 619         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 620         """
 621
 622         comb, sync = m.d.comb, m.d.sync
 623         fast_rf = self.core.regs.rf['fast']
 624         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 625         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 626
 627         with m.FSM() as fsm:
 628
 629             # initiates read of current DEC
 630             with m.State("DEC_READ"):
 631                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 632                 comb += fast_r_dectb.ren.eq(1)
 633                 m.next = "DEC_WRITE"
 634
 635             # waits for DEC read to arrive (1 cycle), updates with new value
 636             with m.State("DEC_WRITE"):
 637                 new_dec = Signal(64)
 638                 # TODO: MSR.LPCR 32-bit decrement mode
 639                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 640                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 641                 comb += fast_w_dectb.wen.eq(1)
 642                 comb += fast_w_dectb.data_i.eq(new_dec)
 643                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 644                 m.next = "TB_READ"
 645
 646             # initiates read of current TB
 647             with m.State("TB_READ"):
 648                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 649                 comb += fast_r_dectb.ren.eq(1)
 650                 m.next = "TB_WRITE"
 651
 652             # waits for read TB to arrive, initiates write of current TB
 653             with m.State("TB_WRITE"):
 654                 new_tb = Signal(64)
 655                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 656                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 657                 comb += fast_w_dectb.wen.eq(1)
 658                 comb += fast_w_dectb.data_i.eq(new_tb)
 659                 m.next = "DEC_READ"
 660
 661         return m
 662
 663     def __iter__(self):
 664         yield from self.pc_i.ports()
 665         yield self.pc_o
 666         yield self.memerr_o
 667         yield from self.core.ports()
 668         yield from self.imem.ports()
 669         yield self.core_bigendian_i
 670         yield self.busy_o
 671
 672     def ports(self):
 673         return list(self)
 674
 675     def external_ports(self):
 676         ports = self.pc_i.ports()
 677         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 678                 ]
 679
 680         if self.jtag_en:
 681             ports += list(self.jtag.external_ports())
 682         else:
 683             # don't add DMI if JTAG is enabled
 684             ports += list(self.dbg.dmi.ports())
 685
 686         ports += list(self.imem.ibus.fields.values())
 687         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 688
 689         if self.sram4x4k:
 690             for sram in self.sram4k:
 691                 ports += list(sram.bus.fields.values())
 692
 693         if self.xics:
 694             ports += list(self.xics_icp.bus.fields.values())
 695             ports += list(self.xics_ics.bus.fields.values())
 696             ports.append(self.int_level_i)
 697
 698         if self.gpio:
 699             ports += list(self.simple_gpio.bus.fields.values())
 700             ports.append(self.gpio_o)
 701
 702         return ports
 703
 704     def ports(self):
 705         return list(self)
 706
 707
 708 class TestIssuer(Elaboratable):
 709     def __init__(self, pspec):
 710         self.ti = TestIssuerInternal(pspec)
 711
 712         self.pll = DummyPLL()
 713
 714         # PLL direct clock or not
 715         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 716         if self.pll_en:
 717             self.pll_18_o = Signal(reset_less=True)
 718
 719     def elaborate(self, platform):
 720         m = Module()
 721         comb = m.d.comb
 722
 723         # TestIssuer runs at direct clock
 724         m.submodules.ti = ti = self.ti
 725         cd_int = ClockDomain("coresync")
 726
 727         if self.pll_en:
 728             # ClockSelect runs at PLL output internal clock rate
 729             m.submodules.pll = pll = self.pll
 730
 731             # add clock domains from PLL
 732             cd_pll = ClockDomain("pllclk")
 733             m.domains += cd_pll
 734
 735             # PLL clock established.  has the side-effect of running clklsel
 736             # at the PLL's speed (see DomainRenamer("pllclk") above)
 737             pllclk = ClockSignal("pllclk")
 738             comb += pllclk.eq(pll.clk_pll_o)
 739
 740             # wire up external 24mhz to PLL
 741             comb += pll.clk_24_i.eq(ClockSignal())
 742
 743             # output 18 mhz PLL test signal
 744             comb += self.pll_18_o.eq(pll.pll_18_o)
 745
 746             # now wire up ResetSignals.  don't mind them being in this domain
 747             pll_rst = ResetSignal("pllclk")
 748             comb += pll_rst.eq(ResetSignal())
 749
 750         # internal clock is set to selector clock-out.  has the side-effect of
 751         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 752         intclk = ClockSignal("coresync")
 753         if self.pll_en:
 754             comb += intclk.eq(pll.clk_pll_o)
 755         else:
 756             comb += intclk.eq(ClockSignal())
 757
 758         return m
 759
 760     def ports(self):
 761         return list(self.ti.ports()) + list(self.pll.ports()) + \
 762                [ClockSignal(), ResetSignal()]
 763
 764     def external_ports(self):
 765         ports = self.ti.external_ports()
 766         ports.append(ClockSignal())
 767         ports.append(ResetSignal())
 768         if self.pll_en:
 769             ports.append(self.pll.clk_sel_i)
 770             ports.append(self.pll_18_o)
 771             ports.append(self.pll.pll_lck_o)
 772         return ports
 773
 774
 775 if __name__ == '__main__':
 776     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 777              'spr': 1,
 778              'div': 1,
 779              'mul': 1,
 780              'shiftrot': 1
 781             }
 782     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 783                          imem_ifacetype='bare_wb',
 784                          addr_wid=48,
 785                          mask_wid=8,
 786                          reg_wid=64,
 787                          units=units)
 788     dut = TestIssuer(pspec)
 789     vl = main(dut, ports=dut.ports(), name="test_issuer")
 790
 791     if len(sys.argv) == 1:
 792         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 793         with open("test_issuer.il", "w") as f:
 794             f.write(vl)