src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156         # pulse to synchronize the simulator at instruction end
 157         self.insn_done = Signal()
 158
 159     def fetch_fsm(self, m, core, pc, svstate, nia,
 160                         fetch_pc_ready_o, fetch_pc_valid_i,
 161                         fetch_insn_valid_o, fetch_insn_ready_i):
 162         """fetch FSM
 163         this FSM performs fetch of raw instruction data, partial-decodes
 164         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 165         read a 2nd 32-bit quantity if that occurs.
 166         """
 167         comb = m.d.comb
 168         sync = m.d.sync
 169         pdecode2 = self.pdecode2
 170         cur_state = self.cur_state
 171         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 172
 173         msr_read = Signal(reset=1)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 comb += fetch_pc_ready_o.eq(1)
 180                 with m.If(fetch_pc_valid_i):
 181                     # instruction allowed to go: start by reading the PC
 182                     # capture the PC and also drop it into Insn Memory
 183                     # we have joined a pair of combinatorial memory
 184                     # lookups together.  this is Generally Bad.
 185                     comb += self.imem.a_pc_i.eq(pc)
 186                     comb += self.imem.a_valid_i.eq(1)
 187                     comb += self.imem.f_valid_i.eq(1)
 188                     sync += cur_state.pc.eq(pc)
 189                     sync += cur_state.svstate.eq(svstate) # and svstate
 190
 191                     # initiate read of MSR. arrives one clock later
 192                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 193                     sync += msr_read.eq(0)
 194
 195                     m.next = "INSN_READ"  # move to "wait for bus" phase
 196
 197             # dummy pause to find out why simulation is not keeping up
 198             with m.State("INSN_READ"):
 199                 # one cycle later, msr/sv read arrives.  valid only once.
 200                 with m.If(~msr_read):
 201                     sync += msr_read.eq(1) # yeah don't read it again
 202                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 203                 with m.If(self.imem.f_busy_o): # zzz...
 204                     # busy: stay in wait-read
 205                     comb += self.imem.a_valid_i.eq(1)
 206                     comb += self.imem.f_valid_i.eq(1)
 207                 with m.Else():
 208                     # not busy: instruction fetched
 209                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 210                     if self.svp64_en:
 211                         svp64 = self.svp64
 212                         # decode the SVP64 prefix, if any
 213                         comb += svp64.raw_opcode_in.eq(insn)
 214                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 215                         # pass the decoded prefix (if any) to PowerDecoder2
 216                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 217                         # calculate the address of the following instruction
 218                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 219                         sync += nia.eq(cur_state.pc + insn_size)
 220                         with m.If(~svp64.is_svp64_mode):
 221                             # with no prefix, store the instruction
 222                             # and hand it directly to the next FSM
 223                             sync += dec_opcode_i.eq(insn)
 224                             m.next = "INSN_READY"
 225                         with m.Else():
 226                             # fetch the rest of the instruction from memory
 227                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 228                             comb += self.imem.a_valid_i.eq(1)
 229                             comb += self.imem.f_valid_i.eq(1)
 230                             m.next = "INSN_READ2"
 231                     else:
 232                         # not SVP64 - 32-bit only
 233                         sync += nia.eq(cur_state.pc + 4)
 234                         sync += dec_opcode_i.eq(insn)
 235                         m.next = "INSN_READY"
 236
 237             with m.State("INSN_READ2"):
 238                 with m.If(self.imem.f_busy_o):  # zzz...
 239                     # busy: stay in wait-read
 240                     comb += self.imem.a_valid_i.eq(1)
 241                     comb += self.imem.f_valid_i.eq(1)
 242                 with m.Else():
 243                     # not busy: instruction fetched
 244                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 245                     sync += dec_opcode_i.eq(insn)
 246                     m.next = "INSN_READY"
 247
 248             with m.State("INSN_READY"):
 249                 # hand over the instruction, to be decoded
 250                 comb += fetch_insn_valid_o.eq(1)
 251                 with m.If(fetch_insn_ready_i):
 252                     m.next = "IDLE"
 253
 254     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 255                   dbg, core_rst,
 256                   fetch_pc_ready_o, fetch_pc_valid_i,
 257                   fetch_insn_valid_o, fetch_insn_ready_i,
 258                   exec_insn_valid_i, exec_insn_ready_o,
 259                   exec_pc_valid_o, exec_pc_ready_i):
 260         """issue FSM
 261
 262         decode / issue FSM.  this interacts with the "fetch" FSM
 263         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 264         (outgoing). also interacts with the "execute" FSM
 265         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 266         (incoming).
 267         SVP64 RM prefixes have already been set up by the
 268         "fetch" phase, so execute is fairly straightforward.
 269         """
 270
 271         comb = m.d.comb
 272         sync = m.d.sync
 273         pdecode2 = self.pdecode2
 274         cur_state = self.cur_state
 275
 276         # temporaries
 277         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 278
 279         # for updating svstate (things like srcstep etc.)
 280         update_svstate = Signal() # set this (below) if updating
 281         new_svstate = SVSTATERec("new_svstate")
 282         comb += new_svstate.eq(cur_state.svstate)
 283
 284         with m.FSM(name="issue_fsm"):
 285
 286             # go fetch the instruction at the current PC
 287             # at this point, there is no instruction running, that
 288             # could inadvertently update the PC.
 289             with m.State("INSN_FETCH"):
 290                 # wait on "core stop" release, before next fetch
 291                 # need to do this here, in case we are in a VL==0 loop
 292                 with m.If(~dbg.core_stop_o & ~core_rst):
 293                     comb += fetch_pc_valid_i.eq(1)
 294                     with m.If(fetch_pc_ready_o):
 295                         m.next = "INSN_WAIT"
 296                 with m.Else():
 297                     comb += core.core_stopped_i.eq(1)
 298                     comb += dbg.core_stopped_i.eq(1)
 299                     # while stopped, allow updating the PC and SVSTATE
 300                     with m.If(self.pc_i.ok):
 301                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 302                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 303                         sync += pc_changed.eq(1)
 304                     with m.If(self.svstate_i.ok):
 305                         comb += new_svstate.eq(self.svstate_i.data)
 306                         comb += update_svstate.eq(1)
 307                         sync += sv_changed.eq(1)
 308
 309             # decode the instruction when it arrives
 310             with m.State("INSN_WAIT"):
 311                 comb += fetch_insn_ready_i.eq(1)
 312                 with m.If(fetch_insn_valid_o):
 313                     # decode the instruction
 314                     sync += core.e.eq(pdecode2.e)
 315                     sync += core.state.eq(cur_state)
 316                     sync += core.raw_insn_i.eq(dec_opcode_i)
 317                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 318                     # loop into INSN_FETCH if it's a vector instruction
 319                     # and VL == 0.  this because VL==0 is a for-loop
 320                     # from 0 to 0 i.e. always, always a NOP.
 321                     cur_vl = cur_state.svstate.vl
 322                     with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
 323                         # update the PC before fetching the next instruction
 324                         # since we are in a VL==0 loop, no instruction was
 325                         # executed that we could be overwriting
 326                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 327                         comb += self.state_w_pc.data_i.eq(nia)
 328                         comb += self.insn_done.eq(1)
 329                         m.next = "INSN_FETCH"
 330                     with m.Else():
 331                         m.next = "INSN_EXECUTE"  # move to "execute"
 332
 333             with m.State("INSN_EXECUTE"):
 334                 comb += exec_insn_valid_i.eq(1)
 335                 with m.If(exec_insn_ready_o):
 336                     m.next = "EXECUTE_WAIT"
 337
 338             with m.State("EXECUTE_WAIT"):
 339                 # wait on "core stop" release, at instruction end
 340                 # need to do this here, in case we are in a VL>1 loop
 341                 with m.If(~dbg.core_stop_o & ~core_rst):
 342                     comb += exec_pc_ready_i.eq(1)
 343                     with m.If(exec_pc_valid_o):
 344                         # precalculate srcstep+1
 345                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 346                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 347                         # was this the last loop iteration?
 348                         is_last = Signal()
 349                         cur_vl = cur_state.svstate.vl
 350                         comb += is_last.eq(next_srcstep == cur_vl)
 351
 352                         # if either PC or SVSTATE were changed by the previous
 353                         # instruction, go directly back to Fetch, without
 354                         # updating either PC or SVSTATE
 355                         with m.If(pc_changed | sv_changed):
 356                             m.next = "INSN_FETCH"
 357
 358                         # also return to Fetch, when no output was a vector
 359                         # (regardless of SRCSTEP and VL), or when the last
 360                         # instruction was really the last one of the VL loop
 361                         with m.Elif(pdecode2.no_out_vec | is_last):
 362                             # before going back to fetch, update the PC state
 363                             # register with the NIA.
 364                             # ok here we are not reading the branch unit.
 365                             # TODO: this just blithely overwrites whatever
 366                             #       pipeline updated the PC
 367                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 368                             comb += self.state_w_pc.data_i.eq(nia)
 369                             # reset SRCSTEP before returning to Fetch
 370                             with m.If(~pdecode2.no_out_vec):
 371                                 comb += new_svstate.srcstep.eq(0)
 372                                 comb += update_svstate.eq(1)
 373                             m.next = "INSN_FETCH"
 374
 375                         # returning to Execute? then, first update SRCSTEP
 376                         with m.Else():
 377                             comb += new_svstate.srcstep.eq(next_srcstep)
 378                             comb += update_svstate.eq(1)
 379                             m.next = "DECODE_SV"
 380
 381                 with m.Else():
 382                     comb += core.core_stopped_i.eq(1)
 383                     comb += dbg.core_stopped_i.eq(1)
 384                     # while stopped, allow updating the PC and SVSTATE
 385                     with m.If(self.pc_i.ok):
 386                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 387                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 388                         sync += pc_changed.eq(1)
 389                     with m.If(self.svstate_i.ok):
 390                         comb += new_svstate.eq(self.svstate_i.data)
 391                         comb += update_svstate.eq(1)
 392                         sync += sv_changed.eq(1)
 393
 394             # need to decode the instruction again, after updating SRCSTEP
 395             # in the previous state.
 396             # mostly a copy of INSN_WAIT, but without the actual wait
 397             with m.State("DECODE_SV"):
 398                 # decode the instruction
 399                 sync += core.e.eq(pdecode2.e)
 400                 sync += core.state.eq(cur_state)
 401                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 402                 m.next = "INSN_EXECUTE"  # move to "execute"
 403
 404         # check if svstate needs updating: if so, write it to State Regfile
 405         with m.If(update_svstate):
 406             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 407             comb += self.state_w_sv.data_i.eq(new_svstate)
 408             sync += cur_state.svstate.eq(new_svstate) # for next clock
 409
 410     def execute_fsm(self, m, core, pc_changed, sv_changed,
 411                     exec_insn_valid_i, exec_insn_ready_o,
 412                     exec_pc_valid_o, exec_pc_ready_i):
 413         """execute FSM
 414
 415         execute FSM. this interacts with the "issue" FSM
 416         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 417         (outgoing). SVP64 RM prefixes have already been set up by the
 418         "issue" phase, so execute is fairly straightforward.
 419         """
 420
 421         comb = m.d.comb
 422         sync = m.d.sync
 423         pdecode2 = self.pdecode2
 424
 425         # temporaries
 426         core_busy_o = core.busy_o                 # core is busy
 427         core_ivalid_i = core.ivalid_i             # instruction is valid
 428         core_issue_i = core.issue_i               # instruction is issued
 429         insn_type = core.e.do.insn_type           # instruction MicroOp type
 430
 431         with m.FSM(name="exec_fsm"):
 432
 433             # waiting for instruction bus (stays there until not busy)
 434             with m.State("INSN_START"):
 435                 comb += exec_insn_ready_o.eq(1)
 436                 with m.If(exec_insn_valid_i):
 437                     comb += core_ivalid_i.eq(1)  # instruction is valid
 438                     comb += core_issue_i.eq(1)  # and issued
 439                     sync += sv_changed.eq(0)
 440                     sync += pc_changed.eq(0)
 441                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 442
 443             # instruction started: must wait till it finishes
 444             with m.State("INSN_ACTIVE"):
 445                 with m.If(insn_type != MicrOp.OP_NOP):
 446                     comb += core_ivalid_i.eq(1) # instruction is valid
 447                 # note changes to PC and SVSTATE
 448                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 449                     sync += sv_changed.eq(1)
 450                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 451                     sync += pc_changed.eq(1)
 452                 with m.If(~core_busy_o): # instruction done!
 453                     comb += exec_pc_valid_o.eq(1)
 454                     with m.If(exec_pc_ready_i):
 455                         comb += self.insn_done.eq(1)
 456                         m.next = "INSN_START"  # back to fetch
 457
 458     def elaborate(self, platform):
 459         m = Module()
 460         comb, sync = m.d.comb, m.d.sync
 461
 462         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 463         m.submodules.imem = imem = self.imem
 464         m.submodules.dbg = dbg = self.dbg
 465         if self.jtag_en:
 466             m.submodules.jtag = jtag = self.jtag
 467             # TODO: UART2GDB mux, here, from external pin
 468             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 469             sync += dbg.dmi.connect_to(jtag.dmi)
 470
 471         cur_state = self.cur_state
 472
 473         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 474         if self.sram4x4k:
 475             for i, sram in enumerate(self.sram4k):
 476                 m.submodules["sram4k_%d" % i] = sram
 477                 comb += sram.enable.eq(self.wb_sram_en)
 478
 479         # XICS interrupt handler
 480         if self.xics:
 481             m.submodules.xics_icp = icp = self.xics_icp
 482             m.submodules.xics_ics = ics = self.xics_ics
 483             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 484             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 485
 486         # GPIO test peripheral
 487         if self.gpio:
 488             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 489
 490         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 491         # XXX causes litex ECP5 test to get wrong idea about input and output
 492         # (but works with verilator sim *sigh*)
 493         #if self.gpio and self.xics:
 494         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 495
 496         # instruction decoder
 497         pdecode = create_pdecode()
 498         m.submodules.dec2 = pdecode2 = self.pdecode2
 499         if self.svp64_en:
 500             m.submodules.svp64 = svp64 = self.svp64
 501
 502         # convenience
 503         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 504         intrf = self.core.regs.rf['int']
 505
 506         # clock delay power-on reset
 507         cd_por  = ClockDomain(reset_less=True)
 508         cd_sync = ClockDomain()
 509         core_sync = ClockDomain("coresync")
 510         m.domains += cd_por, cd_sync, core_sync
 511
 512         ti_rst = Signal(reset_less=True)
 513         delay = Signal(range(4), reset=3)
 514         with m.If(delay != 0):
 515             m.d.por += delay.eq(delay - 1)
 516         comb += cd_por.clk.eq(ClockSignal())
 517
 518         # power-on reset delay
 519         core_rst = ResetSignal("coresync")
 520         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 521         comb += core_rst.eq(ti_rst)
 522
 523         # busy/halted signals from core
 524         comb += self.busy_o.eq(core.busy_o)
 525         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 526
 527         # temporary hack: says "go" immediately for both address gen and ST
 528         l0 = core.l0
 529         ldst = core.fus.fus['ldst0']
 530         st_go_edge = rising_edge(m, ldst.st.rel_o)
 531         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 532         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 533
 534         # PC and instruction from I-Memory
 535         comb += self.pc_o.eq(cur_state.pc)
 536         pc_changed = Signal() # note write to PC
 537         sv_changed = Signal() # note write to SVSTATE
 538
 539         # read the PC
 540         pc = Signal(64, reset_less=True)
 541         pc_ok_delay = Signal()
 542         sync += pc_ok_delay.eq(~self.pc_i.ok)
 543         with m.If(self.pc_i.ok):
 544             # incoming override (start from pc_i)
 545             comb += pc.eq(self.pc_i.data)
 546         with m.Else():
 547             # otherwise read StateRegs regfile for PC...
 548             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 549         # ... but on a 1-clock delay
 550         with m.If(pc_ok_delay):
 551             comb += pc.eq(self.state_r_pc.data_o)
 552
 553         # read svstate
 554         svstate = Signal(64, reset_less=True)
 555         svstate_ok_delay = Signal()
 556         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 557         with m.If(self.svstate_i.ok):
 558             # incoming override (start from svstate__i)
 559             comb += svstate.eq(self.svstate_i.data)
 560         with m.Else():
 561             # otherwise read StateRegs regfile for SVSTATE...
 562             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 563         # ... but on a 1-clock delay
 564         with m.If(svstate_ok_delay):
 565             comb += svstate.eq(self.state_r_sv.data_o)
 566
 567         # don't write pc every cycle
 568         comb += self.state_w_pc.wen.eq(0)
 569         comb += self.state_w_pc.data_i.eq(0)
 570
 571         # don't read msr every cycle
 572         comb += self.state_r_msr.ren.eq(0)
 573
 574         # address of the next instruction, in the absence of a branch
 575         # depends on the instruction size
 576         nia = Signal(64, reset_less=True)
 577
 578         # connect up debug signals
 579         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 580         comb += dbg.terminate_i.eq(core.core_terminate_o)
 581         comb += dbg.state.pc.eq(pc)
 582         comb += dbg.state.svstate.eq(svstate)
 583         comb += dbg.state.msr.eq(cur_state.msr)
 584
 585         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 586         # these are the handshake signals between fetch and decode/execute
 587
 588         # fetch FSM can run as soon as the PC is valid
 589         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 590         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 591
 592         # fetch FSM hands over the instruction to be decoded / issued
 593         fetch_insn_valid_o = Signal()
 594         fetch_insn_ready_i = Signal()
 595
 596         # issue FSM delivers the instruction to the be executed
 597         exec_insn_valid_i = Signal()
 598         exec_insn_ready_o = Signal()
 599
 600         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 601         exec_pc_valid_o = Signal()
 602         exec_pc_ready_i = Signal()
 603
 604         # the FSMs here are perhaps unusual in that they detect conditions
 605         # then "hold" information, combinatorially, for the core
 606         # (as opposed to using sync - which would be on a clock's delay)
 607         # this includes the actual opcode, valid flags and so on.
 608
 609         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 610         # lives.  the ready/valid signalling is used to communicate between
 611         # the three.
 612
 613         self.fetch_fsm(m, core, pc, svstate, nia,
 614                        fetch_pc_ready_o, fetch_pc_valid_i,
 615                        fetch_insn_valid_o, fetch_insn_ready_i)
 616
 617         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 618                        dbg, core_rst,
 619                        fetch_pc_ready_o, fetch_pc_valid_i,
 620                        fetch_insn_valid_o, fetch_insn_ready_i,
 621                        exec_insn_valid_i, exec_insn_ready_o,
 622                        exec_pc_valid_o, exec_pc_ready_i)
 623
 624         self.execute_fsm(m, core, pc_changed, sv_changed,
 625                          exec_insn_valid_i, exec_insn_ready_o,
 626                          exec_pc_valid_o, exec_pc_ready_i)
 627
 628         # this bit doesn't have to be in the FSM: connect up to read
 629         # regfiles on demand from DMI
 630         self.do_dmi(m, dbg)
 631
 632         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 633         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 634         self.tb_dec_fsm(m, cur_state.dec)
 635
 636         return m
 637
 638     def do_dmi(self, m, dbg):
 639         comb = m.d.comb
 640         sync = m.d.sync
 641         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 642         intrf = self.core.regs.rf['int']
 643
 644         with m.If(d_reg.req): # request for regfile access being made
 645             # TODO: error-check this
 646             # XXX should this be combinatorial?  sync better?
 647             if intrf.unary:
 648                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 649             else:
 650                 comb += self.int_r.addr.eq(d_reg.addr)
 651                 comb += self.int_r.ren.eq(1)
 652         d_reg_delay  = Signal()
 653         sync += d_reg_delay.eq(d_reg.req)
 654         with m.If(d_reg_delay):
 655             # data arrives one clock later
 656             comb += d_reg.data.eq(self.int_r.data_o)
 657             comb += d_reg.ack.eq(1)
 658
 659         # sigh same thing for CR debug
 660         with m.If(d_cr.req): # request for regfile access being made
 661             comb += self.cr_r.ren.eq(0b11111111) # enable all
 662         d_cr_delay  = Signal()
 663         sync += d_cr_delay.eq(d_cr.req)
 664         with m.If(d_cr_delay):
 665             # data arrives one clock later
 666             comb += d_cr.data.eq(self.cr_r.data_o)
 667             comb += d_cr.ack.eq(1)
 668
 669         # aaand XER...
 670         with m.If(d_xer.req): # request for regfile access being made
 671             comb += self.xer_r.ren.eq(0b111111) # enable all
 672         d_xer_delay  = Signal()
 673         sync += d_xer_delay.eq(d_xer.req)
 674         with m.If(d_xer_delay):
 675             # data arrives one clock later
 676             comb += d_xer.data.eq(self.xer_r.data_o)
 677             comb += d_xer.ack.eq(1)
 678
 679     def tb_dec_fsm(self, m, spr_dec):
 680         """tb_dec_fsm
 681
 682         this is a FSM for updating either dec or tb.  it runs alternately
 683         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 684         value to DEC, however the regfile has "passthrough" on it so this
 685         *should* be ok.
 686
 687         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 688         """
 689
 690         comb, sync = m.d.comb, m.d.sync
 691         fast_rf = self.core.regs.rf['fast']
 692         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 693         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 694
 695         with m.FSM() as fsm:
 696
 697             # initiates read of current DEC
 698             with m.State("DEC_READ"):
 699                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 700                 comb += fast_r_dectb.ren.eq(1)
 701                 m.next = "DEC_WRITE"
 702
 703             # waits for DEC read to arrive (1 cycle), updates with new value
 704             with m.State("DEC_WRITE"):
 705                 new_dec = Signal(64)
 706                 # TODO: MSR.LPCR 32-bit decrement mode
 707                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 708                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 709                 comb += fast_w_dectb.wen.eq(1)
 710                 comb += fast_w_dectb.data_i.eq(new_dec)
 711                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 712                 m.next = "TB_READ"
 713
 714             # initiates read of current TB
 715             with m.State("TB_READ"):
 716                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 717                 comb += fast_r_dectb.ren.eq(1)
 718                 m.next = "TB_WRITE"
 719
 720             # waits for read TB to arrive, initiates write of current TB
 721             with m.State("TB_WRITE"):
 722                 new_tb = Signal(64)
 723                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 724                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 725                 comb += fast_w_dectb.wen.eq(1)
 726                 comb += fast_w_dectb.data_i.eq(new_tb)
 727                 m.next = "DEC_READ"
 728
 729         return m
 730
 731     def __iter__(self):
 732         yield from self.pc_i.ports()
 733         yield self.pc_o
 734         yield self.memerr_o
 735         yield from self.core.ports()
 736         yield from self.imem.ports()
 737         yield self.core_bigendian_i
 738         yield self.busy_o
 739
 740     def ports(self):
 741         return list(self)
 742
 743     def external_ports(self):
 744         ports = self.pc_i.ports()
 745         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 746                 ]
 747
 748         if self.jtag_en:
 749             ports += list(self.jtag.external_ports())
 750         else:
 751             # don't add DMI if JTAG is enabled
 752             ports += list(self.dbg.dmi.ports())
 753
 754         ports += list(self.imem.ibus.fields.values())
 755         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 756
 757         if self.sram4x4k:
 758             for sram in self.sram4k:
 759                 ports += list(sram.bus.fields.values())
 760
 761         if self.xics:
 762             ports += list(self.xics_icp.bus.fields.values())
 763             ports += list(self.xics_ics.bus.fields.values())
 764             ports.append(self.int_level_i)
 765
 766         if self.gpio:
 767             ports += list(self.simple_gpio.bus.fields.values())
 768             ports.append(self.gpio_o)
 769
 770         return ports
 771
 772     def ports(self):
 773         return list(self)
 774
 775
 776 class TestIssuer(Elaboratable):
 777     def __init__(self, pspec):
 778         self.ti = TestIssuerInternal(pspec)
 779
 780         self.pll = DummyPLL()
 781
 782         # PLL direct clock or not
 783         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 784         if self.pll_en:
 785             self.pll_18_o = Signal(reset_less=True)
 786
 787     def elaborate(self, platform):
 788         m = Module()
 789         comb = m.d.comb
 790
 791         # TestIssuer runs at direct clock
 792         m.submodules.ti = ti = self.ti
 793         cd_int = ClockDomain("coresync")
 794
 795         if self.pll_en:
 796             # ClockSelect runs at PLL output internal clock rate
 797             m.submodules.pll = pll = self.pll
 798
 799             # add clock domains from PLL
 800             cd_pll = ClockDomain("pllclk")
 801             m.domains += cd_pll
 802
 803             # PLL clock established.  has the side-effect of running clklsel
 804             # at the PLL's speed (see DomainRenamer("pllclk") above)
 805             pllclk = ClockSignal("pllclk")
 806             comb += pllclk.eq(pll.clk_pll_o)
 807
 808             # wire up external 24mhz to PLL
 809             comb += pll.clk_24_i.eq(ClockSignal())
 810
 811             # output 18 mhz PLL test signal
 812             comb += self.pll_18_o.eq(pll.pll_18_o)
 813
 814             # now wire up ResetSignals.  don't mind them being in this domain
 815             pll_rst = ResetSignal("pllclk")
 816             comb += pll_rst.eq(ResetSignal())
 817
 818         # internal clock is set to selector clock-out.  has the side-effect of
 819         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 820         intclk = ClockSignal("coresync")
 821         if self.pll_en:
 822             comb += intclk.eq(pll.clk_pll_o)
 823         else:
 824             comb += intclk.eq(ClockSignal())
 825
 826         return m
 827
 828     def ports(self):
 829         return list(self.ti.ports()) + list(self.pll.ports()) + \
 830                [ClockSignal(), ResetSignal()]
 831
 832     def external_ports(self):
 833         ports = self.ti.external_ports()
 834         ports.append(ClockSignal())
 835         ports.append(ResetSignal())
 836         if self.pll_en:
 837             ports.append(self.pll.clk_sel_i)
 838             ports.append(self.pll_18_o)
 839             ports.append(self.pll.pll_lck_o)
 840         return ports
 841
 842
 843 if __name__ == '__main__':
 844     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 845              'spr': 1,
 846              'div': 1,
 847              'mul': 1,
 848              'shiftrot': 1
 849             }
 850     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 851                          imem_ifacetype='bare_wb',
 852                          addr_wid=48,
 853                          mask_wid=8,
 854                          reg_wid=64,
 855                          units=units)
 856     dut = TestIssuer(pspec)
 857     vl = main(dut, ports=dut.ports(), name="test_issuer")
 858
 859     if len(sys.argv) == 1:
 860         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 861         with open("test_issuer.il", "w") as f:
 862             f.write(vl)