src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import StateRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32 from soc.config.state import CoreState
  33
  34 from nmutil.util import rising_edge
  35
  36
  37 class TestIssuer(Elaboratable):
  38     """TestIssuer - reads instructions from TestMemory and issues them
  39
  40     efficiency and speed is not the main goal here: functional correctness is.
  41     """
  42     def __init__(self, pspec):
  43         # main instruction core
  44         self.core = core = NonProductionCore(pspec)
  45
  46         # Test Instruction memory
  47         self.imem = ConfigFetchUnit(pspec).fu
  48         # one-row cache of instruction read
  49         self.iline = Signal(64) # one instruction line
  50         self.iprev_adr = Signal(64) # previous address: if different, do read
  51
  52         # DMI interface
  53         self.dbg = CoreDebug()
  54
  55         # instruction go/monitor
  56         self.pc_o = Signal(64, reset_less=True)
  57         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  58         self.core_bigendian_i = Signal()
  59         self.busy_o = Signal(reset_less=True)
  60         self.memerr_o = Signal(reset_less=True)
  61
  62         # FAST regfile read /write ports for PC and MSR
  63         self.state_r_pc = self.core.regs.rf['state'].r_ports['cia'] # PC rd
  64         self.state_w_pc = self.core.regs.rf['state'].w_ports['d_wr1'] # PC wr
  65         self.state_r_msr = self.core.regs.rf['state'].r_ports['msr'] # MSR rd
  66
  67         # DMI interface access
  68         self.int_r = self.core.regs.rf['int'].r_ports['dmi'] # INT read
  69
  70         # hack method of keeping an eye on whether branch/trap set the PC
  71         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
  72         self.state_nia.wen.name = 'state_nia_wen'
  73
  74     def elaborate(self, platform):
  75         m = Module()
  76         comb, sync = m.d.comb, m.d.sync
  77
  78         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  79         m.submodules.imem = imem = self.imem
  80         m.submodules.dbg = dbg = self.dbg
  81
  82         # convenience
  83         dmi = dbg.dmi
  84         d_reg = dbg.dbg_gpr
  85
  86         # clock delay power-on reset
  87         cd_por  = ClockDomain(reset_less=True)
  88         cd_sync = ClockDomain()
  89         core_sync = ClockDomain("coresync")
  90         m.domains += cd_por, cd_sync, core_sync
  91
  92         delay = Signal(range(4), reset=1)
  93         with m.If(delay != 0):
  94             m.d.por += delay.eq(delay - 1)
  95         comb += cd_por.clk.eq(ClockSignal())
  96         comb += core_sync.clk.eq(ClockSignal())
  97         # XXX TODO: power-on reset delay (later)
  98         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
  99
 100         # busy/halted signals from core
 101         comb += self.busy_o.eq(core.busy_o)
 102         comb += core.bigendian_i.eq(self.core_bigendian_i)
 103
 104         # current state (MSR/PC at the moment
 105         cur_state = CoreState("cur")
 106
 107         # temporary hack: says "go" immediately for both address gen and ST
 108         l0 = core.l0
 109         ldst = core.fus.fus['ldst0']
 110         st_go_edge = rising_edge(m, ldst.st.rel_o)
 111         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 112         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 113
 114         # PC and instruction from I-Memory
 115         current_insn = Signal(32) # current fetched instruction (note sync)
 116         pc_changed = Signal() # note write to PC
 117         comb += self.pc_o.eq(cur_state.pc)
 118         ilatch = Signal(32)
 119
 120         # next instruction (+4 on current)
 121         nia = Signal(64, reset_less=True)
 122         comb += nia.eq(cur_state.pc + 4)
 123
 124         # read the PC
 125         pc = Signal(64, reset_less=True)
 126         with m.If(self.pc_i.ok):
 127             # incoming override (start from pc_i)
 128             comb += pc.eq(self.pc_i.data)
 129         with m.Else():
 130             # otherwise read StateRegs regfile for PC
 131             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 132             comb += pc.eq(self.state_r_pc.data_o)
 133
 134         # don't write pc every cycle
 135         sync += self.state_w_pc.wen.eq(0)
 136         sync += self.state_w_pc.data_i.eq(0)
 137
 138         # don't read msr every cycle
 139         sync += self.state_r_msr.ren.eq(0)
 140
 141         # connect up debug signals
 142         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 143         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 144         comb += core.core_reset_i.eq(dbg.core_rst_o)
 145         comb += dbg.terminate_i.eq(core.core_terminate_o)
 146         comb += dbg.state.pc.eq(pc)
 147         comb += dbg.state.msr.eq(cur_state.msr)
 148
 149         # temporaries
 150         core_busy_o = core.busy_o         # core is busy
 151         core_ivalid_i = core.ivalid_i     # instruction is valid
 152         core_issue_i = core.issue_i       # instruction is issued
 153         core_be_i = core.bigendian_i      # bigendian mode
 154         core_opcode_i = core.raw_opcode_i # raw opcode
 155
 156         insn_type = core.pdecode2.e.do.insn_type
 157         insn_state = core.pdecode2.state
 158
 159         # actually use a nmigen FSM for the first time (w00t)
 160         # this FSM is perhaps unusual in that it detects conditions
 161         # then "holds" information, combinatorially, for the core
 162         # (as opposed to using sync - which would be on a clock's delay)
 163         # this includes the actual opcode, valid flags and so on.
 164         with m.FSM() as fsm:
 165
 166             # waiting (zzz)
 167             with m.State("IDLE"):
 168                 sync += pc_changed.eq(0)
 169                 with m.If(~dbg.core_stop_o):
 170                     # instruction allowed to go: start by reading the PC
 171                     # capture the PC and also drop it into Insn Memory
 172                     # we have joined a pair of combinatorial memory
 173                     # lookups together.  this is Generally Bad.
 174                     comb += self.imem.a_pc_i.eq(pc)
 175                     comb += self.imem.a_valid_i.eq(1)
 176                     comb += self.imem.f_valid_i.eq(1)
 177                     sync += cur_state.pc.eq(pc)
 178
 179                     # read MSR, latch it, and put it in decode "state"
 180                     sync += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 181                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 182
 183                     m.next = "INSN_READ" # move to "wait for bus" phase
 184
 185             # waiting for instruction bus (stays there until not busy)
 186             with m.State("INSN_READ"):
 187                 with m.If(self.imem.f_busy_o): # zzz...
 188                     # busy: stay in wait-read
 189                     comb += self.imem.a_valid_i.eq(1)
 190                     comb += self.imem.f_valid_i.eq(1)
 191                 with m.Else():
 192                     # not busy: instruction fetched
 193                     f_instr_o = self.imem.f_instr_o
 194                     if f_instr_o.width == 32:
 195                         insn = f_instr_o
 196                     else:
 197                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 198                     comb += current_insn.eq(insn)
 199                     comb += core_ivalid_i.eq(1) # instruction is valid
 200                     comb += core_issue_i.eq(1)  # and issued
 201                     comb += core_opcode_i.eq(current_insn) # actual opcode
 202                     sync += ilatch.eq(current_insn) # latch current insn
 203
 204                     # also drop PC and MSR into decode "state"
 205                     comb += insn_state.eq(cur_state)
 206
 207                     m.next = "INSN_ACTIVE" # move to "wait completion"
 208
 209             # instruction started: must wait till it finishes
 210             with m.State("INSN_ACTIVE"):
 211                 with m.If(insn_type != MicrOp.OP_NOP):
 212                     comb += core_ivalid_i.eq(1) # instruction is valid
 213                 comb += core_opcode_i.eq(ilatch) # actual opcode
 214                 comb += insn_state.eq(cur_state)     # and MSR and PC
 215                 with m.If(self.state_nia.wen):
 216                     sync += pc_changed.eq(1)
 217                 with m.If(~core_busy_o): # instruction done!
 218                     # ok here we are not reading the branch unit.  TODO
 219                     # this just blithely overwrites whatever pipeline
 220                     # updated the PC
 221                     with m.If(~pc_changed):
 222                         sync += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 223                         sync += self.state_w_pc.data_i.eq(nia)
 224                     m.next = "IDLE" # back to idle
 225
 226         # this bit doesn't have to be in the FSM: connect up to read
 227         # regfiles on demand from DMI
 228
 229         with m.If(d_reg.req): # request for regfile access being made
 230             # TODO: error-check this
 231             # XXX should this be combinatorial?  sync better?
 232             if hasattr(self.int_r, "ren"):
 233                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 234             else:
 235                 comb += self.int_r.addr.eq(d_reg.addr)
 236                 comb += self.int_r.en.eq(1)
 237             comb += d_reg.data.eq(self.int_r.data_o)
 238             comb += d_reg.ack.eq(1)
 239
 240         return m
 241
 242     def __iter__(self):
 243         yield from self.pc_i.ports()
 244         yield self.pc_o
 245         yield self.memerr_o
 246         yield from self.core.ports()
 247         yield from self.imem.ports()
 248         yield self.core_bigendian_i
 249         yield self.busy_o
 250
 251     def ports(self):
 252         return list(self)
 253
 254     def external_ports(self):
 255         return self.pc_i.ports() + [self.pc_o,
 256                                     self.memerr_o,
 257                                     self.core_bigendian_i,
 258                                     ClockSignal(),
 259                                     ResetSignal(),
 260                                     self.busy_o,
 261                                     ] + \
 262                 list(self.dbg.dmi.ports()) + \
 263                 list(self.imem.ibus.fields.values()) + \
 264                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 265
 266     def ports(self):
 267         return list(self)
 268
 269
 270 if __name__ == '__main__':
 271     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 272              'spr': 1,
 273              'div': 1,
 274              'mul': 1,
 275              'shiftrot': 1
 276             }
 277     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 278                          imem_ifacetype='bare_wb',
 279                          addr_wid=48,
 280                          mask_wid=8,
 281                          reg_wid=64,
 282                          units=units)
 283     dut = TestIssuer(pspec)
 284     vl = main(dut, ports=dut.ports(), name="test_issuer")
 285
 286     if len(sys.argv) == 1:
 287         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 288         with open("test_issuer.il", "w") as f:
 289             f.write(vl)