3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.state
import CoreState
37 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
38 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from nmutil
.util
import rising_edge
43 class TestIssuer(Elaboratable
):
44 """TestIssuer - reads instructions from TestMemory and issues them
46 efficiency and speed is not the main goal here: functional correctness is.
48 def __init__(self
, pspec
):
50 # add interrupt controller?
51 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
53 self
.xics_icp
= XICS_ICP()
54 self
.xics_ics
= XICS_ICS()
55 self
.int_level_i
= self
.xics_ics
.int_level_i
57 # add GPIO peripheral?
58 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
60 self
.simple_gpio
= SimpleGPIO()
61 self
.gpio_o
= self
.simple_gpio
.gpio_o
63 # main instruction core25
64 self
.core
= core
= NonProductionCore(pspec
)
66 # instruction decoder. goes into Trap Record
67 pdecode
= create_pdecode()
68 self
.cur_state
= CoreState("cur") # current state (MSR/PC/EINT)
69 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
70 opkls
=IssuerDecode2ToOperand
)
72 # Test Instruction memory
73 self
.imem
= ConfigFetchUnit(pspec
).fu
74 # one-row cache of instruction read
75 self
.iline
= Signal(64) # one instruction line
76 self
.iprev_adr
= Signal(64) # previous address: if different, do read
79 self
.dbg
= CoreDebug()
82 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
86 # instruction go/monitor
87 self
.pc_o
= Signal(64, reset_less
=True)
88 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
89 self
.core_bigendian_i
= Signal()
90 self
.busy_o
= Signal(reset_less
=True)
91 self
.memerr_o
= Signal(reset_less
=True)
93 # FAST regfile read /write ports for PC, MSR, DEC/TB
94 staterf
= self
.core
.regs
.rf
['state']
95 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
96 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
97 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
99 # DMI interface access
100 intrf
= self
.core
.regs
.rf
['int']
101 crrf
= self
.core
.regs
.rf
['cr']
102 xerrf
= self
.core
.regs
.rf
['xer']
103 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
104 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
105 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
107 # hack method of keeping an eye on whether branch/trap set the PC
108 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
109 self
.state_nia
.wen
.name
= 'state_nia_wen'
111 def elaborate(self
, platform
):
113 comb
, sync
= m
.d
.comb
, m
.d
.sync
115 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
116 m
.submodules
.imem
= imem
= self
.imem
117 m
.submodules
.dbg
= dbg
= self
.dbg
119 m
.submodules
.jtag
= jtag
= self
.jtag
120 # TODO: UART2GDB mux, here, from external pin
121 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
122 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
124 cur_state
= self
.cur_state
126 # XICS interrupt handler
128 m
.submodules
.xics_icp
= icp
= self
.xics_icp
129 m
.submodules
.xics_ics
= ics
= self
.xics_ics
130 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
131 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
133 # GPIO test peripheral
135 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
137 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
138 if self
.gpio
and self
.xics
:
139 comb
+= self
.int_level_i
[15].eq(simple_gpio
.gpio_o
[0])
141 # instruction decoder
142 pdecode
= create_pdecode()
143 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
146 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
147 intrf
= self
.core
.regs
.rf
['int']
149 # clock delay power-on reset
150 cd_por
= ClockDomain(reset_less
=True)
151 cd_sync
= ClockDomain()
152 core_sync
= ClockDomain("coresync")
153 m
.domains
+= cd_por
, cd_sync
, core_sync
155 delay
= Signal(range(4), reset
=3)
156 with m
.If(delay
!= 0):
157 m
.d
.por
+= delay
.eq(delay
- 1)
158 comb
+= cd_por
.clk
.eq(ClockSignal())
159 comb
+= core_sync
.clk
.eq(ClockSignal())
160 # power-on reset delay
161 comb
+= core
.core_reset_i
.eq(delay
!= 0 | dbg
.core_rst_o
)
163 # busy/halted signals from core
164 comb
+= self
.busy_o
.eq(core
.busy_o
)
165 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
167 # temporary hack: says "go" immediately for both address gen and ST
169 ldst
= core
.fus
.fus
['ldst0']
170 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
171 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
172 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
174 # PC and instruction from I-Memory
175 pc_changed
= Signal() # note write to PC
176 comb
+= self
.pc_o
.eq(cur_state
.pc
)
179 # next instruction (+4 on current)
180 nia
= Signal(64, reset_less
=True)
181 comb
+= nia
.eq(cur_state
.pc
+ 4)
184 pc
= Signal(64, reset_less
=True)
185 pc_ok_delay
= Signal()
186 sync
+= pc_ok_delay
.eq(~self
.pc_i
.ok
)
187 with m
.If(self
.pc_i
.ok
):
188 # incoming override (start from pc_i)
189 comb
+= pc
.eq(self
.pc_i
.data
)
191 # otherwise read StateRegs regfile for PC...
192 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
193 # ... but on a 1-clock delay
194 with m
.If(pc_ok_delay
):
195 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
197 # don't write pc every cycle
198 comb
+= self
.state_w_pc
.wen
.eq(0)
199 comb
+= self
.state_w_pc
.data_i
.eq(0)
201 # don't read msr every cycle
202 comb
+= self
.state_r_msr
.ren
.eq(0)
203 msr_read
= Signal(reset
=1)
205 # connect up debug signals
206 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
207 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
208 comb
+= dbg
.state
.pc
.eq(pc
)
209 #comb += dbg.state.pc.eq(cur_state.pc)
210 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
213 core_busy_o
= core
.busy_o
# core is busy
214 core_ivalid_i
= core
.ivalid_i
# instruction is valid
215 core_issue_i
= core
.issue_i
# instruction is issued
216 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
218 insn_type
= core
.e
.do
.insn_type
220 # actually use a nmigen FSM for the first time (w00t)
221 # this FSM is perhaps unusual in that it detects conditions
222 # then "holds" information, combinatorially, for the core
223 # (as opposed to using sync - which would be on a clock's delay)
224 # this includes the actual opcode, valid flags and so on.
228 with m
.State("IDLE"):
229 sync
+= pc_changed
.eq(0)
231 sync
+= core
.raw_insn_i
.eq(0)
232 sync
+= core
.bigendian_i
.eq(0)
233 with m
.If(~dbg
.core_stop_o
& ~core
.core_reset_i
):
234 # instruction allowed to go: start by reading the PC
235 # capture the PC and also drop it into Insn Memory
236 # we have joined a pair of combinatorial memory
237 # lookups together. this is Generally Bad.
238 comb
+= self
.imem
.a_pc_i
.eq(pc
)
239 comb
+= self
.imem
.a_valid_i
.eq(1)
240 comb
+= self
.imem
.f_valid_i
.eq(1)
241 sync
+= cur_state
.pc
.eq(pc
)
243 # initiate read of MSR. arrives one clock later
244 comb
+= self
.state_r_msr
.ren
.eq(1<<StateRegs
.MSR
)
245 sync
+= msr_read
.eq(0)
247 m
.next
= "INSN_READ" # move to "wait for bus" phase
249 comb
+= core
.core_stopped_i
.eq(1)
250 comb
+= dbg
.core_stopped_i
.eq(1)
252 # dummy pause to find out why simulation is not keeping up
253 with m
.State("INSN_READ"):
254 # one cycle later, msr read arrives. valid only once.
255 with m
.If(~msr_read
):
256 sync
+= msr_read
.eq(1) # yeah don't read it again
257 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
258 with m
.If(self
.imem
.f_busy_o
): # zzz...
259 # busy: stay in wait-read
260 comb
+= self
.imem
.a_valid_i
.eq(1)
261 comb
+= self
.imem
.f_valid_i
.eq(1)
263 # not busy: instruction fetched
264 f_instr_o
= self
.imem
.f_instr_o
265 if f_instr_o
.width
== 32:
268 insn
= f_instr_o
.word_select(cur_state
.pc
[2], 32)
269 comb
+= dec_opcode_i
.eq(insn
) # actual opcode
270 sync
+= core
.e
.eq(pdecode2
.e
)
271 sync
+= core
.state
.eq(cur_state
)
272 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
273 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
274 sync
+= ilatch
.eq(insn
) # latch current insn
275 # also drop PC and MSR into decode "state"
276 m
.next
= "INSN_START" # move to "start"
278 # waiting for instruction bus (stays there until not busy)
279 with m
.State("INSN_START"):
280 comb
+= core_ivalid_i
.eq(1) # instruction is valid
281 comb
+= core_issue_i
.eq(1) # and issued
283 m
.next
= "INSN_ACTIVE" # move to "wait completion"
285 # instruction started: must wait till it finishes
286 with m
.State("INSN_ACTIVE"):
287 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
288 comb
+= core_ivalid_i
.eq(1) # instruction is valid
289 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
290 sync
+= pc_changed
.eq(1)
291 with m
.If(~core_busy_o
): # instruction done!
292 # ok here we are not reading the branch unit. TODO
293 # this just blithely overwrites whatever pipeline
295 with m
.If(~pc_changed
):
296 comb
+= self
.state_w_pc
.wen
.eq(1<<StateRegs
.PC
)
297 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
299 sync
+= core
.raw_insn_i
.eq(0)
300 sync
+= core
.bigendian_i
.eq(0)
301 m
.next
= "IDLE" # back to idle
303 # this bit doesn't have to be in the FSM: connect up to read
304 # regfiles on demand from DMI
305 with m
.If(d_reg
.req
): # request for regfile access being made
306 # TODO: error-check this
307 # XXX should this be combinatorial? sync better?
309 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
311 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
312 comb
+= self
.int_r
.ren
.eq(1)
313 d_reg_delay
= Signal()
314 sync
+= d_reg_delay
.eq(d_reg
.req
)
315 with m
.If(d_reg_delay
):
316 # data arrives one clock later
317 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
318 comb
+= d_reg
.ack
.eq(1)
320 # sigh same thing for CR debug
321 with m
.If(d_cr
.req
): # request for regfile access being made
322 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
323 d_cr_delay
= Signal()
324 sync
+= d_cr_delay
.eq(d_cr
.req
)
325 with m
.If(d_cr_delay
):
326 # data arrives one clock later
327 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
328 comb
+= d_cr
.ack
.eq(1)
331 with m
.If(d_xer
.req
): # request for regfile access being made
332 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
333 d_xer_delay
= Signal()
334 sync
+= d_xer_delay
.eq(d_xer
.req
)
335 with m
.If(d_xer_delay
):
336 # data arrives one clock later
337 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
338 comb
+= d_xer
.ack
.eq(1)
340 # DEC and TB inc/dec FSM
341 self
.tb_dec_fsm(m
, cur_state
.dec
)
345 def tb_dec_fsm(self
, m
, spr_dec
):
348 this is a FSM for updating either dec or tb. it runs alternately
349 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
350 value to DEC, however the regfile has "passthrough" on it so this
353 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
356 comb
, sync
= m
.d
.comb
, m
.d
.sync
357 fast_rf
= self
.core
.regs
.rf
['fast']
358 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
359 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
363 # initiates read of current DEC
364 with m
.State("DEC_READ"):
365 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
366 comb
+= fast_r_dectb
.ren
.eq(1)
369 # waits for DEC read to arrive (1 cycle), updates with new value
370 with m
.State("DEC_WRITE"):
372 # TODO: MSR.LPCR 32-bit decrement mode
373 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
374 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
375 comb
+= fast_w_dectb
.wen
.eq(1)
376 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
377 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
380 # initiates read of current TB
381 with m
.State("TB_READ"):
382 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
383 comb
+= fast_r_dectb
.ren
.eq(1)
386 # waits for read TB to arrive, initiates write of current TB
387 with m
.State("TB_WRITE"):
389 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
390 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
391 comb
+= fast_w_dectb
.wen
.eq(1)
392 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
398 yield from self
.pc_i
.ports()
401 yield from self
.core
.ports()
402 yield from self
.imem
.ports()
403 yield self
.core_bigendian_i
409 def external_ports(self
):
410 ports
= self
.pc_i
.ports()
411 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
412 ClockSignal(), ResetSignal(),
416 ports
+= list(self
.jtag
.external_ports())
418 # don't add DMI if JTAG is enabled
419 ports
+= list(self
.dbg
.dmi
.ports())
421 ports
+= list(self
.imem
.ibus
.fields
.values())
422 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
425 ports
+= list(self
.xics_icp
.bus
.fields
.values())
426 ports
+= list(self
.xics_ics
.bus
.fields
.values())
427 ports
.append(self
.int_level_i
)
430 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
431 ports
.append(self
.gpio_o
)
439 if __name__
== '__main__':
440 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
446 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
447 imem_ifacetype
='bare_wb',
452 dut
= TestIssuer(pspec
)
453 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
455 if len(sys
.argv
) == 1:
456 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
457 with
open("test_issuer.il", "w") as f
: