src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20 from nmigen.cli import main
  21 import sys
  22
  23 from soc.decoder.decode2execute1 import Data
  24 from soc.experiment.testmem import TestMemory # test only for instructions
  25 from soc.regfile.regfiles import FastRegs
  26 from soc.simple.core import NonProductionCore
  27 from soc.config.test.test_loadstore import TestMemPspec
  28 from soc.config.ifetch import ConfigFetchUnit
  29 from soc.decoder.power_enums import MicrOp
  30
  31
  32 class TestIssuer(Elaboratable):
  33     """TestIssuer - reads instructions from TestMemory and issues them
  34
  35     efficiency and speed is not the main goal here: functional correctness is.
  36     """
  37     def __init__(self, pspec):
  38         # main instruction core
  39         self.core = core = NonProductionCore(pspec)
  40
  41         # Test Instruction memory
  42         self.imem = ConfigFetchUnit(pspec).fu
  43         # one-row cache of instruction read
  44         self.iline = Signal(64) # one instruction line
  45         self.iprev_adr = Signal(64) # previous address: if different, do read
  46
  47         # instruction go/monitor
  48         self.go_insn_i = Signal(reset_less=True)
  49         self.pc_o = Signal(64, reset_less=True)
  50         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  51         self.core_start_i = Signal()
  52         self.core_bigendian_i = Signal()
  53         self.busy_o = Signal(reset_less=True)
  54         self.halted_o = Signal(reset_less=True)
  55         self.memerr_o = Signal(reset_less=True)
  56
  57         # FAST regfile read /write ports for PC and MSR
  58         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['d_rd1'] # PC rd
  59         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  60         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['d_rd2'] # MSR rd
  61
  62         # hack method of keeping an eye on whether branch/trap set the PC
  63         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  64         self.fast_nia.wen.name = 'fast_nia_wen'
  65
  66     def elaborate(self, platform):
  67         m = Module()
  68         comb, sync = m.d.comb, m.d.sync
  69
  70         m.submodules.core = core = self.core
  71         m.submodules.imem = imem = self.imem
  72
  73         # busy/halted signals from core
  74         comb += self.busy_o.eq(core.busy_o)
  75         comb += self.halted_o.eq(core.core_terminated_o)
  76         comb += self.core_start_i.eq(core.core_start_i)
  77         comb += self.core_bigendian_i.eq(core.bigendian_i)
  78
  79         # temporary hack: says "go" immediately for both address gen and ST
  80         l0 = core.l0
  81         ldst = core.fus.fus['ldst0']
  82         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  83         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  84
  85         # PC and instruction from I-Memory
  86         current_insn = Signal(32) # current fetched instruction (note sync)
  87         cur_pc = Signal(64) # current PC (note it is reset/sync)
  88         pc_changed = Signal() # note write to PC
  89         comb += self.pc_o.eq(cur_pc)
  90         ilatch = Signal(32)
  91
  92         # MSR (temp and latched)
  93         cur_msr = Signal(64) # current MSR (note it is reset/sync)
  94         msr = Signal(64, reset_less=True)
  95
  96         # next instruction (+4 on current)
  97         nia = Signal(64, reset_less=True)
  98         comb += nia.eq(cur_pc + 4)
  99
 100         # temporaries
 101         core_busy_o = core.busy_o         # core is busy
 102         core_ivalid_i = core.ivalid_i     # instruction is valid
 103         core_issue_i = core.issue_i       # instruction is issued
 104         core_be_i = core.bigendian_i      # bigendian mode
 105         core_opcode_i = core.raw_opcode_i # raw opcode
 106
 107         insn_type = core.pdecode2.e.do.insn_type
 108         insn_msr = core.pdecode2.msr
 109
 110         # only run if not in halted state
 111         with m.If(~core.core_terminated_o):
 112
 113             # actually use a nmigen FSM for the first time (w00t)
 114             # this FSM is perhaps unusual in that it detects conditions
 115             # then "holds" information, combinatorially, for the core
 116             # (as opposed to using sync - which would be on a clock's delay)
 117             # this includes the actual opcode, valid flags and so on.
 118             with m.FSM() as fsm:
 119
 120                 # waiting (zzz)
 121                 with m.State("IDLE"):
 122                     sync += pc_changed.eq(0)
 123                     with m.If(self.go_insn_i):
 124                         # instruction allowed to go: start by reading the PC
 125                         pc = Signal(64, reset_less=True)
 126                         with m.If(self.pc_i.ok):
 127                             # incoming override (start from pc_i)
 128                             comb += pc.eq(self.pc_i.data)
 129                         with m.Else():
 130                             # otherwise read FastRegs regfile for PC
 131                             comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 132                             comb += pc.eq(self.fast_r_pc.data_o)
 133                         # capture the PC and also drop it into Insn Memory
 134                         # we have joined a pair of combinatorial memory
 135                         # lookups together.  this is Generally Bad.
 136                         comb += self.imem.a_pc_i.eq(pc)
 137                         comb += self.imem.a_valid_i.eq(1)
 138                         comb += self.imem.f_valid_i.eq(1)
 139                         sync += cur_pc.eq(pc)
 140                         m.next = "INSN_READ" # move to "wait for bus" phase
 141
 142                 # waiting for instruction bus (stays there until not busy)
 143                 with m.State("INSN_READ"):
 144                     with m.If(self.imem.f_busy_o): # zzz...
 145                         # busy: stay in wait-read
 146                         comb += self.imem.a_valid_i.eq(1)
 147                         comb += self.imem.f_valid_i.eq(1)
 148                     with m.Else():
 149                         # not busy: instruction fetched
 150                         insn = self.imem.f_instr_o.word_select(cur_pc[2], 32)
 151                         comb += current_insn.eq(insn)
 152                         comb += core_ivalid_i.eq(1) # instruction is valid
 153                         comb += core_issue_i.eq(1)  # and issued
 154                         comb += core_opcode_i.eq(current_insn) # actual opcode
 155                         sync += ilatch.eq(current_insn) # latch current insn
 156
 157                         # read MSR
 158                         comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 159                         comb += msr.eq(self.fast_r_msr.data_o)
 160                         comb += insn_msr.eq(msr)
 161                         sync += cur_msr.eq(msr) # latch current MSR
 162
 163                         m.next = "INSN_ACTIVE" # move to "wait completion"
 164
 165                 # instruction started: must wait till it finishes
 166                 with m.State("INSN_ACTIVE"):
 167                     with m.If(core.core_terminated_o):
 168                         m.next = "IDLE" # back to idle, immediately (OP_ATTN)
 169                     with m.Else():
 170                         with m.If(insn_type != MicrOp.OP_NOP):
 171                             comb += core_ivalid_i.eq(1) # instruction is valid
 172                         comb += core_opcode_i.eq(ilatch) # actual opcode
 173                         comb += insn_msr.eq(cur_msr)     # and MSR
 174                         with m.If(self.fast_nia.wen):
 175                             sync += pc_changed.eq(1)
 176                         with m.If(~core_busy_o): # instruction done!
 177                             # ok here we are not reading the branch unit.  TODO
 178                             # this just blithely overwrites whatever pipeline
 179                             # updated the PC
 180                             with m.If(~pc_changed):
 181                                 comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 182                                 comb += self.fast_w_pc.data_i.eq(nia)
 183                             m.next = "IDLE" # back to idle
 184
 185         return m
 186
 187     def __iter__(self):
 188         yield from self.pc_i.ports()
 189         yield self.pc_o
 190         yield self.go_insn_i
 191         yield self.memerr_o
 192         yield from self.core.ports()
 193         yield from self.imem.ports()
 194
 195     def ports(self):
 196         return list(self)
 197
 198
 199 if __name__ == '__main__':
 200     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 201              'spr': 1,
 202              'mul': 1,
 203              'shiftrot': 1}
 204     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 205                          imem_ifacetype='bare_wb',
 206                          addr_wid=48,
 207                          mask_wid=8,
 208                          reg_wid=64,
 209                          units=units)
 210     dut = TestIssuer(pspec)
 211     vl = main(dut, ports=dut.ports(), name="test_issuer")
 212
 213     if len(sys.argv) == 1:
 214         vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
 215         with open("test_issuer.il", "w") as f:
 216             f.write(vl)