src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import FastRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32
  33
  34 class TestIssuer(Elaboratable):
  35     """TestIssuer - reads instructions from TestMemory and issues them
  36
  37     efficiency and speed is not the main goal here: functional correctness is.
  38     """
  39     def __init__(self, pspec):
  40         # main instruction core
  41         self.core = core = NonProductionCore(pspec)
  42
  43         # Test Instruction memory
  44         self.imem = ConfigFetchUnit(pspec).fu
  45         # one-row cache of instruction read
  46         self.iline = Signal(64) # one instruction line
  47         self.iprev_adr = Signal(64) # previous address: if different, do read
  48
  49         # DMI interface
  50         self.dbg = CoreDebug()
  51         self.dmi = self.dbg.dmi
  52
  53         # instruction go/monitor
  54         self.pc_o = Signal(64, reset_less=True)
  55         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  56         self.core_bigendian_i = Signal()
  57         self.busy_o = Signal(reset_less=True)
  58         self.memerr_o = Signal(reset_less=True)
  59
  60         # FAST regfile read /write ports for PC and MSR
  61         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
  62         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  63         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
  64
  65         # hack method of keeping an eye on whether branch/trap set the PC
  66         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  67         self.fast_nia.wen.name = 'fast_nia_wen'
  68
  69     def elaborate(self, platform):
  70         m = Module()
  71         comb, sync = m.d.comb, m.d.sync
  72
  73         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  74         m.submodules.imem = imem = self.imem
  75         m.submodules.dbg = dbg = self.dbg
  76
  77         # clock delay power-on reset
  78         cd_por  = ClockDomain(reset_less=True)
  79         cd_sync = ClockDomain()
  80         core_sync = ClockDomain("coresync")
  81         m.domains += cd_por, cd_sync, core_sync
  82
  83         delay = Signal(range(4), reset=1)
  84         with m.If(delay != 0):
  85             m.d.por += delay.eq(delay - 1)
  86         comb += cd_por.clk.eq(ClockSignal())
  87         comb += core_sync.clk.eq(ClockSignal())
  88         # XXX TODO: power-on reset delay (later)
  89         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
  90         comb += core.core_reset_i.eq(dbg.core_rst_o)
  91
  92         # busy/halted signals from core
  93         comb += self.busy_o.eq(core.busy_o)
  94         comb += core.bigendian_i.eq(self.core_bigendian_i)
  95
  96         # temporary hack: says "go" immediately for both address gen and ST
  97         l0 = core.l0
  98         ldst = core.fus.fus['ldst0']
  99         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 100         m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 101
 102         # PC and instruction from I-Memory
 103         current_insn = Signal(32) # current fetched instruction (note sync)
 104         cur_pc = Signal(64) # current PC (note it is reset/sync)
 105         pc_changed = Signal() # note write to PC
 106         comb += self.pc_o.eq(cur_pc)
 107         ilatch = Signal(32)
 108
 109         # MSR (temp and latched)
 110         cur_msr = Signal(64) # current MSR (note it is reset/sync)
 111         msr = Signal(64, reset_less=True)
 112
 113         # next instruction (+4 on current)
 114         nia = Signal(64, reset_less=True)
 115         comb += nia.eq(cur_pc + 4)
 116
 117         # connect up debug signals
 118         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 119         # TODO comb += core.reset_i.eq(dbg.core_rst_o)
 120         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 121         comb += dbg.terminate_i.eq(core.core_terminate_o)
 122         comb += dbg.state.pc.eq(cur_pc)
 123         comb += dbg.state.msr.eq(cur_msr)
 124
 125         # temporaries
 126         core_busy_o = core.busy_o         # core is busy
 127         core_ivalid_i = core.ivalid_i     # instruction is valid
 128         core_issue_i = core.issue_i       # instruction is issued
 129         core_be_i = core.bigendian_i      # bigendian mode
 130         core_opcode_i = core.raw_opcode_i # raw opcode
 131
 132         insn_type = core.pdecode2.e.do.insn_type
 133         insn_msr = core.pdecode2.msr
 134         insn_cia = core.pdecode2.cia
 135
 136         # actually use a nmigen FSM for the first time (w00t)
 137         # this FSM is perhaps unusual in that it detects conditions
 138         # then "holds" information, combinatorially, for the core
 139         # (as opposed to using sync - which would be on a clock's delay)
 140         # this includes the actual opcode, valid flags and so on.
 141         with m.FSM() as fsm:
 142
 143             # waiting (zzz)
 144             with m.State("IDLE"):
 145                 sync += pc_changed.eq(0)
 146                 with m.If(~dbg.core_stop_o):
 147                     # instruction allowed to go: start by reading the PC
 148                     pc = Signal(64, reset_less=True)
 149                     with m.If(self.pc_i.ok):
 150                         # incoming override (start from pc_i)
 151                         comb += pc.eq(self.pc_i.data)
 152                     with m.Else():
 153                         # otherwise read FastRegs regfile for PC
 154                         comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 155                         comb += pc.eq(self.fast_r_pc.data_o)
 156                     # capture the PC and also drop it into Insn Memory
 157                     # we have joined a pair of combinatorial memory
 158                     # lookups together.  this is Generally Bad.
 159                     comb += self.imem.a_pc_i.eq(pc)
 160                     comb += self.imem.a_valid_i.eq(1)
 161                     comb += self.imem.f_valid_i.eq(1)
 162                     sync += cur_pc.eq(pc)
 163                     m.next = "INSN_READ" # move to "wait for bus" phase
 164
 165             # waiting for instruction bus (stays there until not busy)
 166             with m.State("INSN_READ"):
 167                 with m.If(self.imem.f_busy_o): # zzz...
 168                     # busy: stay in wait-read
 169                     comb += self.imem.a_valid_i.eq(1)
 170                     comb += self.imem.f_valid_i.eq(1)
 171                 with m.Else():
 172                     # not busy: instruction fetched
 173                     f_instr_o = self.imem.f_instr_o
 174                     if f_instr_o.width == 32:
 175                         insn = f_instr_o
 176                     else:
 177                         insn = f_instr_o.word_select(cur_pc[2], 32)
 178                     comb += current_insn.eq(insn)
 179                     comb += core_ivalid_i.eq(1) # instruction is valid
 180                     comb += core_issue_i.eq(1)  # and issued
 181                     comb += core_opcode_i.eq(current_insn) # actual opcode
 182                     sync += ilatch.eq(current_insn) # latch current insn
 183
 184                     # read MSR, latch it, and put it in decode "state"
 185                     comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 186                     comb += msr.eq(self.fast_r_msr.data_o)
 187                     comb += insn_msr.eq(msr)
 188                     sync += cur_msr.eq(msr) # latch current MSR
 189
 190                     # also drop PC into decode "state"
 191                     comb += insn_cia.eq(cur_pc)
 192
 193                     m.next = "INSN_ACTIVE" # move to "wait completion"
 194
 195             # instruction started: must wait till it finishes
 196             with m.State("INSN_ACTIVE"):
 197                 with m.If(insn_type != MicrOp.OP_NOP):
 198                     comb += core_ivalid_i.eq(1) # instruction is valid
 199                 comb += core_opcode_i.eq(ilatch) # actual opcode
 200                 comb += insn_msr.eq(cur_msr)     # and MSR
 201                 comb += insn_cia.eq(cur_pc)     # and PC
 202                 with m.If(self.fast_nia.wen):
 203                     sync += pc_changed.eq(1)
 204                 with m.If(~core_busy_o): # instruction done!
 205                     # ok here we are not reading the branch unit.  TODO
 206                     # this just blithely overwrites whatever pipeline
 207                     # updated the PC
 208                     with m.If(~pc_changed):
 209                         comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 210                         comb += self.fast_w_pc.data_i.eq(nia)
 211                     m.next = "IDLE" # back to idle
 212
 213         return m
 214
 215     def __iter__(self):
 216         yield from self.pc_i.ports()
 217         yield self.pc_o
 218         yield self.memerr_o
 219         yield from self.core.ports()
 220         yield from self.imem.ports()
 221         yield self.core_bigendian_i
 222         yield self.busy_o
 223
 224     def ports(self):
 225         return list(self)
 226
 227     def external_ports(self):
 228         return self.pc_i.ports() + [self.pc_o,
 229                                     self.memerr_o,
 230                                     self.busy_o,
 231                                     ] + \
 232                 list(self.dbg.dmi.ports()) + \
 233                 list(self.imem.ibus.fields.values()) + \
 234                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 235
 236     def ports(self):
 237         return list(self)
 238
 239
 240 if __name__ == '__main__':
 241     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 242              'spr': 1,
 243              'mul': 1,
 244              'shiftrot': 1}
 245     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 246                          imem_ifacetype='bare_wb',
 247                          addr_wid=48,
 248                          mask_wid=8,
 249                          reg_wid=64,
 250                          units=units)
 251     dut = TestIssuer(pspec)
 252     vl = main(dut, ports=dut.ports(), name="test_issuer")
 253
 254     if len(sys.argv) == 1:
 255         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 256         with open("test_issuer.il", "w") as f:
 257             f.write(vl)