3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from FastRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.decode2execute1
import Data
25 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
26 from soc
.regfile
.regfiles
import FastRegs
27 from soc
.simple
.core
import NonProductionCore
28 from soc
.config
.test
.test_loadstore
import TestMemPspec
29 from soc
.config
.ifetch
import ConfigFetchUnit
30 from soc
.decoder
.power_enums
import MicrOp
31 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
32 from soc
.config
.state
import CoreState
34 from nmutil
.util
import rising_edge
37 class TestIssuer(Elaboratable
):
38 """TestIssuer - reads instructions from TestMemory and issues them
40 efficiency and speed is not the main goal here: functional correctness is.
42 def __init__(self
, pspec
):
43 # main instruction core
44 self
.core
= core
= NonProductionCore(pspec
)
46 # Test Instruction memory
47 self
.imem
= ConfigFetchUnit(pspec
).fu
48 # one-row cache of instruction read
49 self
.iline
= Signal(64) # one instruction line
50 self
.iprev_adr
= Signal(64) # previous address: if different, do read
53 self
.dbg
= CoreDebug()
55 # instruction go/monitor
56 self
.pc_o
= Signal(64, reset_less
=True)
57 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
58 self
.core_bigendian_i
= Signal()
59 self
.busy_o
= Signal(reset_less
=True)
60 self
.memerr_o
= Signal(reset_less
=True)
62 # FAST regfile read /write ports for PC and MSR
63 self
.fast_r_pc
= self
.core
.regs
.rf
['fast'].r_ports
['cia'] # PC rd
64 self
.fast_w_pc
= self
.core
.regs
.rf
['fast'].w_ports
['d_wr1'] # PC wr
65 self
.fast_r_msr
= self
.core
.regs
.rf
['fast'].r_ports
['msr'] # MSR rd
67 # DMI interface access
68 self
.int_r
= self
.core
.regs
.rf
['int'].r_ports
['dmi'] # INT read
70 # hack method of keeping an eye on whether branch/trap set the PC
71 self
.fast_nia
= self
.core
.regs
.rf
['fast'].w_ports
['nia']
72 self
.fast_nia
.wen
.name
= 'fast_nia_wen'
74 def elaborate(self
, platform
):
76 comb
, sync
= m
.d
.comb
, m
.d
.sync
78 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
79 m
.submodules
.imem
= imem
= self
.imem
80 m
.submodules
.dbg
= dbg
= self
.dbg
86 # clock delay power-on reset
87 cd_por
= ClockDomain(reset_less
=True)
88 cd_sync
= ClockDomain()
89 core_sync
= ClockDomain("coresync")
90 m
.domains
+= cd_por
, cd_sync
, core_sync
92 delay
= Signal(range(4), reset
=1)
93 with m
.If(delay
!= 0):
94 m
.d
.por
+= delay
.eq(delay
- 1)
95 comb
+= cd_por
.clk
.eq(ClockSignal())
96 comb
+= core_sync
.clk
.eq(ClockSignal())
97 # XXX TODO: power-on reset delay (later)
98 #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
100 # busy/halted signals from core
101 comb
+= self
.busy_o
.eq(core
.busy_o
)
102 comb
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
104 # current state (MSR/PC at the moment
105 cur_state
= CoreState("cur")
107 # temporary hack: says "go" immediately for both address gen and ST
109 ldst
= core
.fus
.fus
['ldst0']
110 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
111 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
112 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
114 # PC and instruction from I-Memory
115 current_insn
= Signal(32) # current fetched instruction (note sync)
116 pc_changed
= Signal() # note write to PC
117 comb
+= self
.pc_o
.eq(cur_state
.pc
)
120 # next instruction (+4 on current)
121 nia
= Signal(64, reset_less
=True)
122 comb
+= nia
.eq(cur_state
.pc
+ 4)
125 pc
= Signal(64, reset_less
=True)
126 with m
.If(self
.pc_i
.ok
):
127 # incoming override (start from pc_i)
128 comb
+= pc
.eq(self
.pc_i
.data
)
130 # otherwise read FastRegs regfile for PC
131 comb
+= self
.fast_r_pc
.ren
.eq(1<<FastRegs
.PC
)
132 comb
+= pc
.eq(self
.fast_r_pc
.data_o
)
134 # connect up debug signals
135 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
136 comb
+= core
.core_stopped_i
.eq(dbg
.core_stop_o
)
137 comb
+= core
.core_reset_i
.eq(dbg
.core_rst_o
)
138 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
139 comb
+= dbg
.state
.pc
.eq(pc
)
140 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
143 core_busy_o
= core
.busy_o
# core is busy
144 core_ivalid_i
= core
.ivalid_i
# instruction is valid
145 core_issue_i
= core
.issue_i
# instruction is issued
146 core_be_i
= core
.bigendian_i
# bigendian mode
147 core_opcode_i
= core
.raw_opcode_i
# raw opcode
149 insn_type
= core
.pdecode2
.e
.do
.insn_type
150 insn_state
= core
.pdecode2
.state
152 # don't read msr every cycle
153 sync
+= self
.fast_r_msr
.ren
.eq(0)
155 # actually use a nmigen FSM for the first time (w00t)
156 # this FSM is perhaps unusual in that it detects conditions
157 # then "holds" information, combinatorially, for the core
158 # (as opposed to using sync - which would be on a clock's delay)
159 # this includes the actual opcode, valid flags and so on.
163 with m
.State("IDLE"):
164 sync
+= pc_changed
.eq(0)
165 with m
.If(~dbg
.core_stop_o
):
166 # instruction allowed to go: start by reading the PC
167 # capture the PC and also drop it into Insn Memory
168 # we have joined a pair of combinatorial memory
169 # lookups together. this is Generally Bad.
170 comb
+= self
.imem
.a_pc_i
.eq(pc
)
171 comb
+= self
.imem
.a_valid_i
.eq(1)
172 comb
+= self
.imem
.f_valid_i
.eq(1)
173 sync
+= cur_state
.pc
.eq(pc
)
175 # read MSR, latch it, and put it in decode "state"
176 sync
+= self
.fast_r_msr
.ren
.eq(1<<FastRegs
.MSR
)
177 sync
+= cur_state
.msr
.eq(self
.fast_r_msr
.data_o
)
179 m
.next
= "INSN_READ" # move to "wait for bus" phase
181 # waiting for instruction bus (stays there until not busy)
182 with m
.State("INSN_READ"):
183 with m
.If(self
.imem
.f_busy_o
): # zzz...
184 # busy: stay in wait-read
185 comb
+= self
.imem
.a_valid_i
.eq(1)
186 comb
+= self
.imem
.f_valid_i
.eq(1)
188 # not busy: instruction fetched
189 f_instr_o
= self
.imem
.f_instr_o
190 if f_instr_o
.width
== 32:
193 insn
= f_instr_o
.word_select(cur_state
.pc
[2], 32)
194 comb
+= current_insn
.eq(insn
)
195 comb
+= core_ivalid_i
.eq(1) # instruction is valid
196 comb
+= core_issue_i
.eq(1) # and issued
197 comb
+= core_opcode_i
.eq(current_insn
) # actual opcode
198 sync
+= ilatch
.eq(current_insn
) # latch current insn
200 # also drop PC and MSR into decode "state"
201 comb
+= insn_state
.eq(cur_state
)
203 m
.next
= "INSN_ACTIVE" # move to "wait completion"
205 # instruction started: must wait till it finishes
206 with m
.State("INSN_ACTIVE"):
207 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
208 comb
+= core_ivalid_i
.eq(1) # instruction is valid
209 comb
+= core_opcode_i
.eq(ilatch
) # actual opcode
210 comb
+= insn_state
.eq(cur_state
) # and MSR and PC
211 with m
.If(self
.fast_nia
.wen
):
212 sync
+= pc_changed
.eq(1)
213 with m
.If(~core_busy_o
): # instruction done!
214 # ok here we are not reading the branch unit. TODO
215 # this just blithely overwrites whatever pipeline
217 with m
.If(~pc_changed
):
218 comb
+= self
.fast_w_pc
.wen
.eq(1<<FastRegs
.PC
)
219 comb
+= self
.fast_w_pc
.data_i
.eq(nia
)
220 m
.next
= "IDLE" # back to idle
222 # this bit doesn't have to be in the FSM: connect up to read
223 # regfiles on demand from DMI
225 with m
.If(d_reg
.req
): # request for regfile access being made
226 # TODO: error-check this
227 # XXX should this be combinatorial? sync better?
228 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
229 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
230 comb
+= d_reg
.ack
.eq(1)
235 yield from self
.pc_i
.ports()
238 yield from self
.core
.ports()
239 yield from self
.imem
.ports()
240 yield self
.core_bigendian_i
246 def external_ports(self
):
247 return self
.pc_i
.ports() + [self
.pc_o
,
249 self
.core_bigendian_i
,
254 list(self
.dbg
.dmi
.ports()) + \
255 list(self
.imem
.ibus
.fields
.values()) + \
256 list(self
.core
.l0
.cmpi
.lsmem
.lsi
.dbus
.fields
.values())
262 if __name__
== '__main__':
263 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
268 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
269 imem_ifacetype
='bare_wb',
274 dut
= TestIssuer(pspec
)
275 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
277 if len(sys
.argv
) == 1:
278 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
279 with
open("test_issuer.il", "w") as f
: