src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2
  26 from soc.decoder.decode2execute1 import Data
  27 from soc.experiment.testmem import TestMemory # test only for instructions
  28 from soc.regfile.regfiles import StateRegs
  29 from soc.simple.core import NonProductionCore
  30 from soc.config.test.test_loadstore import TestMemPspec
  31 from soc.config.ifetch import ConfigFetchUnit
  32 from soc.decoder.power_enums import MicrOp
  33 from soc.debug.dmi import CoreDebug, DMIInterface
  34 from soc.config.state import CoreState
  35 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  36 from soc.bus.simple_gpio import SimpleGPIO
  37
  38 from nmutil.util import rising_edge
  39
  40
  41 class TestIssuer(Elaboratable):
  42     """TestIssuer - reads instructions from TestMemory and issues them
  43
  44     efficiency and speed is not the main goal here: functional correctness is.
  45     """
  46     def __init__(self, pspec):
  47
  48         # add interrupt controller?
  49         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  50         if self.xics:
  51             self.xics_icp = XICS_ICP()
  52             self.xics_ics = XICS_ICS()
  53             self.int_level_i = self.xics_ics.int_level_i
  54
  55         # add GPIO peripheral?
  56         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  57         if self.gpio:
  58             self.simple_gpio = SimpleGPIO()
  59             self.gpio_o = self.simple_gpio.gpio_o
  60
  61         # main instruction core
  62         self.core = core = NonProductionCore(pspec)
  63
  64         # instruction decoder
  65         pdecode = create_pdecode()
  66         self.pdecode2 = PowerDecode2(pdecode)   # decoder
  67
  68         # Test Instruction memory
  69         self.imem = ConfigFetchUnit(pspec).fu
  70         # one-row cache of instruction read
  71         self.iline = Signal(64) # one instruction line
  72         self.iprev_adr = Signal(64) # previous address: if different, do read
  73
  74         # DMI interface
  75         self.dbg = CoreDebug()
  76
  77         # instruction go/monitor
  78         self.pc_o = Signal(64, reset_less=True)
  79         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  80         self.core_bigendian_i = Signal()
  81         self.busy_o = Signal(reset_less=True)
  82         self.memerr_o = Signal(reset_less=True)
  83
  84         # FAST regfile read /write ports for PC and MSR
  85         staterf = self.core.regs.rf['state']
  86         self.state_r_pc = staterf.r_ports['cia'] # PC rd
  87         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
  88         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
  89
  90         # DMI interface access
  91         intrf = self.core.regs.rf['int']
  92         crrf = self.core.regs.rf['cr']
  93         xerrf = self.core.regs.rf['xer']
  94         self.int_r = intrf.r_ports['dmi'] # INT read
  95         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
  96         self.xer_r = xerrf.r_ports['full_xer'] # XER read
  97
  98         # hack method of keeping an eye on whether branch/trap set the PC
  99         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 100         self.state_nia.wen.name = 'state_nia_wen'
 101
 102     def elaborate(self, platform):
 103         m = Module()
 104         comb, sync = m.d.comb, m.d.sync
 105
 106         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 107         m.submodules.imem = imem = self.imem
 108         m.submodules.dbg = dbg = self.dbg
 109
 110         # current state (MSR/PC at the moment
 111         cur_state = CoreState("cur")
 112
 113         # XICS interrupt handler
 114         if self.xics:
 115             m.submodules.xics_icp = icp = self.xics_icp
 116             m.submodules.xics_ics = ics = self.xics_ics
 117             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 118             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 119
 120         # GPIO test peripheral
 121         if self.gpio:
 122             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 123
 124         # connect one GPIO output to ICS bit 5 (like in microwatt soc.vhdl)
 125         if self.gpio and self.xics:
 126             comb += self.int_level_i[5].eq(simple_gpio.gpio_o[0])
 127
 128         # instruction decoder
 129         pdecode = create_pdecode()
 130         m.submodules.dec2 = pdecode2 = self.pdecode2
 131
 132         # convenience
 133         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 134         intrf = self.core.regs.rf['int']
 135
 136         # clock delay power-on reset
 137         cd_por  = ClockDomain(reset_less=True)
 138         cd_sync = ClockDomain()
 139         core_sync = ClockDomain("coresync")
 140         m.domains += cd_por, cd_sync, core_sync
 141
 142         delay = Signal(range(4), reset=3)
 143         with m.If(delay != 0):
 144             m.d.por += delay.eq(delay - 1)
 145         comb += cd_por.clk.eq(ClockSignal())
 146         comb += core_sync.clk.eq(ClockSignal())
 147         # power-on reset delay
 148         comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
 149
 150         # busy/halted signals from core
 151         comb += self.busy_o.eq(core.busy_o)
 152         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 153
 154         # temporary hack: says "go" immediately for both address gen and ST
 155         l0 = core.l0
 156         ldst = core.fus.fus['ldst0']
 157         st_go_edge = rising_edge(m, ldst.st.rel_o)
 158         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 159         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 160
 161         # PC and instruction from I-Memory
 162         pc_changed = Signal() # note write to PC
 163         comb += self.pc_o.eq(cur_state.pc)
 164         ilatch = Signal(32)
 165
 166         # next instruction (+4 on current)
 167         nia = Signal(64, reset_less=True)
 168         comb += nia.eq(cur_state.pc + 4)
 169
 170         # read the PC
 171         pc = Signal(64, reset_less=True)
 172         pc_ok_delay = Signal()
 173         sync += pc_ok_delay.eq(~self.pc_i.ok)
 174         with m.If(self.pc_i.ok):
 175             # incoming override (start from pc_i)
 176             comb += pc.eq(self.pc_i.data)
 177         with m.Else():
 178             # otherwise read StateRegs regfile for PC...
 179             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 180         # ... but on a 1-clock delay
 181         with m.If(pc_ok_delay):
 182             comb += pc.eq(self.state_r_pc.data_o)
 183
 184         # don't write pc every cycle
 185         comb += self.state_w_pc.wen.eq(0)
 186         comb += self.state_w_pc.data_i.eq(0)
 187
 188         # don't read msr every cycle
 189         comb += self.state_r_msr.ren.eq(0)
 190         msr_read = Signal(reset=1)
 191
 192         # connect up debug signals
 193         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 194         comb += dbg.terminate_i.eq(core.core_terminate_o)
 195         comb += dbg.state.pc.eq(pc)
 196         #comb += dbg.state.pc.eq(cur_state.pc)
 197         comb += dbg.state.msr.eq(cur_state.msr)
 198
 199         # temporaries
 200         core_busy_o = core.busy_o                 # core is busy
 201         core_ivalid_i = core.ivalid_i             # instruction is valid
 202         core_issue_i = core.issue_i               # instruction is issued
 203         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 204
 205         insn_type = core.e.do.insn_type
 206         dec_state = pdecode2.state
 207
 208         # actually use a nmigen FSM for the first time (w00t)
 209         # this FSM is perhaps unusual in that it detects conditions
 210         # then "holds" information, combinatorially, for the core
 211         # (as opposed to using sync - which would be on a clock's delay)
 212         # this includes the actual opcode, valid flags and so on.
 213         with m.FSM() as fsm:
 214
 215             # waiting (zzz)
 216             with m.State("IDLE"):
 217                 sync += pc_changed.eq(0)
 218                 sync += core.e.eq(0)
 219                 with m.If(~dbg.core_stop_o & ~core.core_reset_i):
 220                     # instruction allowed to go: start by reading the PC
 221                     # capture the PC and also drop it into Insn Memory
 222                     # we have joined a pair of combinatorial memory
 223                     # lookups together.  this is Generally Bad.
 224                     comb += self.imem.a_pc_i.eq(pc)
 225                     comb += self.imem.a_valid_i.eq(1)
 226                     comb += self.imem.f_valid_i.eq(1)
 227                     sync += cur_state.pc.eq(pc)
 228
 229                     # initiate read of MSR
 230                     comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 231                     sync += msr_read.eq(0)
 232
 233                     m.next = "INSN_READ" # move to "wait for bus" phase
 234                 with m.Else():
 235                     comb += core.core_stopped_i.eq(1)
 236                     comb += dbg.core_stopped_i.eq(1)
 237
 238             # dummy pause to find out why simulation is not keeping up
 239             with m.State("INSN_READ"):
 240                 # one cycle later, msr read arrives
 241                 with m.If(~msr_read):
 242                     sync += msr_read.eq(1)
 243                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 244                 with m.If(self.imem.f_busy_o): # zzz...
 245                     # busy: stay in wait-read
 246                     comb += self.imem.a_valid_i.eq(1)
 247                     comb += self.imem.f_valid_i.eq(1)
 248                 with m.Else():
 249                     # not busy: instruction fetched
 250                     f_instr_o = self.imem.f_instr_o
 251                     if f_instr_o.width == 32:
 252                         insn = f_instr_o
 253                     else:
 254                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 255                     comb += dec_opcode_i.eq(insn) # actual opcode
 256                     comb += dec_state.eq(cur_state)
 257                     sync += core.e.eq(pdecode2.e)
 258                     sync += ilatch.eq(insn) # latch current insn
 259                     # also drop PC and MSR into decode "state"
 260                     m.next = "INSN_START" # move to "start"
 261
 262             # waiting for instruction bus (stays there until not busy)
 263             with m.State("INSN_START"):
 264                 comb += core_ivalid_i.eq(1) # instruction is valid
 265                 comb += core_issue_i.eq(1)  # and issued
 266
 267
 268                 m.next = "INSN_ACTIVE" # move to "wait completion"
 269
 270             # instruction started: must wait till it finishes
 271             with m.State("INSN_ACTIVE"):
 272                 with m.If(insn_type != MicrOp.OP_NOP):
 273                     comb += core_ivalid_i.eq(1) # instruction is valid
 274                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 275                     sync += pc_changed.eq(1)
 276                 with m.If(~core_busy_o): # instruction done!
 277                     # ok here we are not reading the branch unit.  TODO
 278                     # this just blithely overwrites whatever pipeline
 279                     # updated the PC
 280                     with m.If(~pc_changed):
 281                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 282                         comb += self.state_w_pc.data_i.eq(nia)
 283                     sync += core.e.eq(0)
 284                     m.next = "IDLE" # back to idle
 285
 286         # this bit doesn't have to be in the FSM: connect up to read
 287         # regfiles on demand from DMI
 288         with m.If(d_reg.req): # request for regfile access being made
 289             # TODO: error-check this
 290             # XXX should this be combinatorial?  sync better?
 291             if intrf.unary:
 292                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 293             else:
 294                 comb += self.int_r.addr.eq(d_reg.addr)
 295                 comb += self.int_r.ren.eq(1)
 296         d_reg_delay  = Signal()
 297         sync += d_reg_delay.eq(d_reg.req)
 298         with m.If(d_reg_delay):
 299             # data arrives one clock later
 300             comb += d_reg.data.eq(self.int_r.data_o)
 301             comb += d_reg.ack.eq(1)
 302
 303         # sigh same thing for CR debug
 304         with m.If(d_cr.req): # request for regfile access being made
 305             comb += self.cr_r.ren.eq(0b11111111) # enable all
 306         d_cr_delay  = Signal()
 307         sync += d_cr_delay.eq(d_cr.req)
 308         with m.If(d_cr_delay):
 309             # data arrives one clock later
 310             comb += d_cr.data.eq(self.cr_r.data_o)
 311             comb += d_cr.ack.eq(1)
 312
 313         # aaand XER...
 314         with m.If(d_xer.req): # request for regfile access being made
 315             comb += self.xer_r.ren.eq(0b111111) # enable all
 316         d_xer_delay  = Signal()
 317         sync += d_xer_delay.eq(d_xer.req)
 318         with m.If(d_xer_delay):
 319             # data arrives one clock later
 320             comb += d_xer.data.eq(self.xer_r.data_o)
 321             comb += d_xer.ack.eq(1)
 322
 323         return m
 324
 325     def __iter__(self):
 326         yield from self.pc_i.ports()
 327         yield self.pc_o
 328         yield self.memerr_o
 329         yield from self.core.ports()
 330         yield from self.imem.ports()
 331         yield self.core_bigendian_i
 332         yield self.busy_o
 333
 334     def ports(self):
 335         return list(self)
 336
 337     def external_ports(self):
 338         ports = self.pc_i.ports()
 339         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 340                   ClockSignal(), ResetSignal(),
 341                 ]
 342         ports += list(self.dbg.dmi.ports())
 343         ports += list(self.imem.ibus.fields.values())
 344         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 345
 346         if self.xics:
 347             ports += list(self.xics_icp.bus.fields.values())
 348             ports += list(self.xics_ics.bus.fields.values())
 349             ports.append(self.int_level_i)
 350
 351         if self.gpio:
 352             ports += list(self.simple_gpio.bus.fields.values())
 353             ports.append(self.gpio_o)
 354
 355         return ports
 356
 357     def ports(self):
 358         return list(self)
 359
 360
 361 if __name__ == '__main__':
 362     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 363              'spr': 1,
 364              'div': 1,
 365              'mul': 1,
 366              'shiftrot': 1
 367             }
 368     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 369                          imem_ifacetype='bare_wb',
 370                          addr_wid=48,
 371                          mask_wid=8,
 372                          reg_wid=64,
 373                          units=units)
 374     dut = TestIssuer(pspec)
 375     vl = main(dut, ports=dut.ports(), name="test_issuer")
 376
 377     if len(sys.argv) == 1:
 378         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 379         with open("test_issuer.il", "w") as f:
 380             f.write(vl)