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TWI enabled in JTAG boundary scan
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from soc.decoder.power_decoder import create_pdecode
27 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from soc.decoder.decode2execute1 import Data
30 from soc.experiment.testmem import TestMemory # test only for instructions
31 from soc.regfile.regfiles import StateRegs, FastRegs
32 from soc.simple.core import NonProductionCore
33 from soc.config.test.test_loadstore import TestMemPspec
34 from soc.config.ifetch import ConfigFetchUnit
35 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
36 SVP64PredMode)
37 from soc.debug.dmi import CoreDebug, DMIInterface
38 from soc.debug.jtag import JTAG
39 from soc.config.pinouts import get_pinspecs
40 from soc.config.state import CoreState
41 from soc.interrupts.xics import XICS_ICP, XICS_ICS
42 from soc.bus.simple_gpio import SimpleGPIO
43 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
44 from soc.clock.select import ClockSelect
45 from soc.clock.dummypll import DummyPLL
46 from soc.sv.svstate import SVSTATERec
47
48
49 from nmutil.util import rising_edge
50
51 def get_insn(f_instr_o, pc):
52 if f_instr_o.width == 32:
53 return f_instr_o
54 else:
55 # 64-bit: bit 2 of pc decides which word to select
56 return f_instr_o.word_select(pc[2], 32)
57
58 # gets state input or reads from state regfile
59 def state_get(m, state_i, name, regfile, regnum):
60 comb = m.d.comb
61 sync = m.d.sync
62 # read the PC
63 res = Signal(64, reset_less=True, name=name)
64 res_ok_delay = Signal(name="%s_ok_delay" % name)
65 sync += res_ok_delay.eq(~state_i.ok)
66 with m.If(state_i.ok):
67 # incoming override (start from pc_i)
68 comb += res.eq(state_i.data)
69 with m.Else():
70 # otherwise read StateRegs regfile for PC...
71 comb += regfile.ren.eq(1<<regnum)
72 # ... but on a 1-clock delay
73 with m.If(res_ok_delay):
74 comb += res.eq(regfile.data_o)
75 return res
76
77 def get_predint(m, mask, name):
78 """decode SVP64 predicate integer mask field to reg number and invert
79 this is identical to the equivalent function in ISACaller except that
80 it doesn't read the INT directly, it just decodes "what needs to be done"
81 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
82
83 * all1s is set to indicate that no mask is to be applied.
84 * regread indicates the GPR register number to be read
85 * invert is set to indicate that the register value is to be inverted
86 * unary indicates that the contents of the register is to be shifted 1<<r3
87 """
88 comb = m.d.comb
89 regread = Signal(5, name=name+"regread")
90 invert = Signal(name=name+"invert")
91 unary = Signal(name=name+"unary")
92 all1s = Signal(name=name+"all1s")
93 with m.Switch(mask):
94 with m.Case(SVP64PredInt.ALWAYS.value):
95 comb += all1s.eq(1) # use 0b1111 (all ones)
96 with m.Case(SVP64PredInt.R3_UNARY.value):
97 comb += regread.eq(3)
98 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
99 with m.Case(SVP64PredInt.R3.value):
100 comb += regread.eq(3)
101 with m.Case(SVP64PredInt.R3_N.value):
102 comb += regread.eq(3)
103 comb += invert.eq(1)
104 with m.Case(SVP64PredInt.R10.value):
105 comb += regread.eq(10)
106 with m.Case(SVP64PredInt.R10_N.value):
107 comb += regread.eq(10)
108 comb += invert.eq(1)
109 with m.Case(SVP64PredInt.R30.value):
110 comb += regread.eq(30)
111 with m.Case(SVP64PredInt.R30_N.value):
112 comb += regread.eq(30)
113 comb += invert.eq(1)
114 return regread, invert, unary, all1s
115
116 def get_predcr(m, mask, name):
117 """decode SVP64 predicate CR to reg number field and invert status
118 this is identical to _get_predcr in ISACaller
119 """
120 comb = m.d.comb
121 idx = Signal(2, name=name+"idx")
122 invert = Signal(name=name+"crinvert")
123 with m.Switch(mask):
124 with m.Case(SVP64PredCR.LT.value):
125 comb += idx.eq(0)
126 comb += invert.eq(1)
127 with m.Case(SVP64PredCR.GE.value):
128 comb += idx.eq(0)
129 comb += invert.eq(0)
130 with m.Case(SVP64PredCR.GT.value):
131 comb += idx.eq(1)
132 comb += invert.eq(1)
133 with m.Case(SVP64PredCR.LE.value):
134 comb += idx.eq(1)
135 comb += invert.eq(0)
136 with m.Case(SVP64PredCR.EQ.value):
137 comb += idx.eq(2)
138 comb += invert.eq(1)
139 with m.Case(SVP64PredCR.NE.value):
140 comb += idx.eq(1)
141 comb += invert.eq(0)
142 with m.Case(SVP64PredCR.SO.value):
143 comb += idx.eq(3)
144 comb += invert.eq(1)
145 with m.Case(SVP64PredCR.NS.value):
146 comb += idx.eq(3)
147 comb += invert.eq(0)
148 return idx, invert
149
150
151 class TestIssuerInternal(Elaboratable):
152 """TestIssuer - reads instructions from TestMemory and issues them
153
154 efficiency and speed is not the main goal here: functional correctness
155 and code clarity is. optimisations (which almost 100% interfere with
156 easy understanding) come later.
157 """
158 def __init__(self, pspec):
159
160 # test is SVP64 is to be enabled
161 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
162
163 # and if regfiles are reduced
164 self.regreduce_en = (hasattr(pspec, "regreduce") and
165 (pspec.regreduce == True))
166
167 # JTAG interface. add this right at the start because if it's
168 # added it *modifies* the pspec, by adding enable/disable signals
169 # for parts of the rest of the core
170 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
171 if self.jtag_en:
172 # XXX MUST keep this up-to-date with litex, and
173 # soc-cocotb-sim, and err.. all needs sorting out, argh
174 subset = ['uart',
175 'mtwi',
176 'eint', 'gpio', 'mspi0',
177 # 'mspi1', - disabled for now
178 # 'pwm', 'sd0', - disabled for now
179 'sdr']
180 self.jtag = JTAG(get_pinspecs(subset=subset))
181 # add signals to pspec to enable/disable icache and dcache
182 # (or data and intstruction wishbone if icache/dcache not included)
183 # https://bugs.libre-soc.org/show_bug.cgi?id=520
184 # TODO: do we actually care if these are not domain-synchronised?
185 # honestly probably not.
186 pspec.wb_icache_en = self.jtag.wb_icache_en
187 pspec.wb_dcache_en = self.jtag.wb_dcache_en
188 self.wb_sram_en = self.jtag.wb_sram_en
189 else:
190 self.wb_sram_en = Const(1)
191
192 # add 4k sram blocks?
193 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
194 pspec.sram4x4kblock == True)
195 if self.sram4x4k:
196 self.sram4k = []
197 for i in range(4):
198 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
199 features={'err'}))
200
201 # add interrupt controller?
202 self.xics = hasattr(pspec, "xics") and pspec.xics == True
203 if self.xics:
204 self.xics_icp = XICS_ICP()
205 self.xics_ics = XICS_ICS()
206 self.int_level_i = self.xics_ics.int_level_i
207
208 # add GPIO peripheral?
209 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
210 if self.gpio:
211 self.simple_gpio = SimpleGPIO()
212 self.gpio_o = self.simple_gpio.gpio_o
213
214 # main instruction core. suitable for prototyping / demo only
215 self.core = core = NonProductionCore(pspec)
216
217 # instruction decoder. goes into Trap Record
218 pdecode = create_pdecode()
219 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
220 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
221 opkls=IssuerDecode2ToOperand,
222 svp64_en=self.svp64_en,
223 regreduce_en=self.regreduce_en)
224 if self.svp64_en:
225 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
226
227 # Test Instruction memory
228 self.imem = ConfigFetchUnit(pspec).fu
229
230 # DMI interface
231 self.dbg = CoreDebug()
232
233 # instruction go/monitor
234 self.pc_o = Signal(64, reset_less=True)
235 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
236 self.svstate_i = Data(32, "svstate_i") # ditto
237 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
238 self.busy_o = Signal(reset_less=True)
239 self.memerr_o = Signal(reset_less=True)
240
241 # STATE regfile read /write ports for PC, MSR, SVSTATE
242 staterf = self.core.regs.rf['state']
243 self.state_r_pc = staterf.r_ports['cia'] # PC rd
244 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
245 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
246 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
247 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
248
249 # DMI interface access
250 intrf = self.core.regs.rf['int']
251 crrf = self.core.regs.rf['cr']
252 xerrf = self.core.regs.rf['xer']
253 self.int_r = intrf.r_ports['dmi'] # INT read
254 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
255 self.xer_r = xerrf.r_ports['full_xer'] # XER read
256
257 if self.svp64_en:
258 # for predication
259 self.int_pred = intrf.r_ports['pred'] # INT predicate read
260 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
261
262 # hack method of keeping an eye on whether branch/trap set the PC
263 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
264 self.state_nia.wen.name = 'state_nia_wen'
265
266 # pulse to synchronize the simulator at instruction end
267 self.insn_done = Signal()
268
269 if self.svp64_en:
270 # store copies of predicate masks
271 self.srcmask = Signal(64)
272 self.dstmask = Signal(64)
273
274 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
275 fetch_pc_ready_o, fetch_pc_valid_i,
276 fetch_insn_valid_o, fetch_insn_ready_i):
277 """fetch FSM
278
279 this FSM performs fetch of raw instruction data, partial-decodes
280 it 32-bit at a time to detect SVP64 prefixes, and will optionally
281 read a 2nd 32-bit quantity if that occurs.
282 """
283 comb = m.d.comb
284 sync = m.d.sync
285 pdecode2 = self.pdecode2
286 cur_state = self.cur_state
287 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
288
289 msr_read = Signal(reset=1)
290
291 with m.FSM(name='fetch_fsm'):
292
293 # waiting (zzz)
294 with m.State("IDLE"):
295 comb += fetch_pc_ready_o.eq(1)
296 with m.If(fetch_pc_valid_i):
297 # instruction allowed to go: start by reading the PC
298 # capture the PC and also drop it into Insn Memory
299 # we have joined a pair of combinatorial memory
300 # lookups together. this is Generally Bad.
301 comb += self.imem.a_pc_i.eq(pc)
302 comb += self.imem.a_valid_i.eq(1)
303 comb += self.imem.f_valid_i.eq(1)
304 sync += cur_state.pc.eq(pc)
305 sync += cur_state.svstate.eq(svstate) # and svstate
306
307 # initiate read of MSR. arrives one clock later
308 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
309 sync += msr_read.eq(0)
310
311 m.next = "INSN_READ" # move to "wait for bus" phase
312
313 # dummy pause to find out why simulation is not keeping up
314 with m.State("INSN_READ"):
315 # one cycle later, msr/sv read arrives. valid only once.
316 with m.If(~msr_read):
317 sync += msr_read.eq(1) # yeah don't read it again
318 sync += cur_state.msr.eq(self.state_r_msr.data_o)
319 with m.If(self.imem.f_busy_o): # zzz...
320 # busy: stay in wait-read
321 comb += self.imem.a_valid_i.eq(1)
322 comb += self.imem.f_valid_i.eq(1)
323 with m.Else():
324 # not busy: instruction fetched
325 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
326 if self.svp64_en:
327 svp64 = self.svp64
328 # decode the SVP64 prefix, if any
329 comb += svp64.raw_opcode_in.eq(insn)
330 comb += svp64.bigendian.eq(self.core_bigendian_i)
331 # pass the decoded prefix (if any) to PowerDecoder2
332 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
333 # remember whether this is a prefixed instruction, so
334 # the FSM can readily loop when VL==0
335 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
336 # calculate the address of the following instruction
337 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
338 sync += nia.eq(cur_state.pc + insn_size)
339 with m.If(~svp64.is_svp64_mode):
340 # with no prefix, store the instruction
341 # and hand it directly to the next FSM
342 sync += dec_opcode_i.eq(insn)
343 m.next = "INSN_READY"
344 with m.Else():
345 # fetch the rest of the instruction from memory
346 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
347 comb += self.imem.a_valid_i.eq(1)
348 comb += self.imem.f_valid_i.eq(1)
349 m.next = "INSN_READ2"
350 else:
351 # not SVP64 - 32-bit only
352 sync += nia.eq(cur_state.pc + 4)
353 sync += dec_opcode_i.eq(insn)
354 m.next = "INSN_READY"
355
356 with m.State("INSN_READ2"):
357 with m.If(self.imem.f_busy_o): # zzz...
358 # busy: stay in wait-read
359 comb += self.imem.a_valid_i.eq(1)
360 comb += self.imem.f_valid_i.eq(1)
361 with m.Else():
362 # not busy: instruction fetched
363 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
364 sync += dec_opcode_i.eq(insn)
365 m.next = "INSN_READY"
366 # TODO: probably can start looking at pdecode2.rm_dec
367 # here or maybe even in INSN_READ state, if svp64_mode
368 # detected, in order to trigger - and wait for - the
369 # predicate reading.
370 if self.svp64_en:
371 pmode = pdecode2.rm_dec.predmode
372 """
373 if pmode != SVP64PredMode.ALWAYS.value:
374 fire predicate loading FSM and wait before
375 moving to INSN_READY
376 else:
377 sync += self.srcmask.eq(-1) # set to all 1s
378 sync += self.dstmask.eq(-1) # set to all 1s
379 m.next = "INSN_READY"
380 """
381
382 with m.State("INSN_READY"):
383 # hand over the instruction, to be decoded
384 comb += fetch_insn_valid_o.eq(1)
385 with m.If(fetch_insn_ready_i):
386 m.next = "IDLE"
387
388 def fetch_predicate_fsm(self, m,
389 pred_insn_valid_i, pred_insn_ready_o,
390 pred_mask_valid_o, pred_mask_ready_i):
391 """fetch_predicate_fsm - obtains (constructs in the case of CR)
392 src/dest predicate masks
393
394 https://bugs.libre-soc.org/show_bug.cgi?id=617
395 the predicates can be read here, by using IntRegs r_ports['pred']
396 or CRRegs r_ports['pred']. in the case of CRs it will have to
397 be done through multiple reads, extracting one relevant at a time.
398 later, a faster way would be to use the 32-bit-wide CR port but
399 this is more complex decoding, here. equivalent code used in
400 ISACaller is "from soc.decoder.isa.caller import get_predcr"
401
402 note: this ENTIRE FSM is not to be called when svp64 is disabled
403 """
404 comb = m.d.comb
405 sync = m.d.sync
406 pdecode2 = self.pdecode2
407 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
408 predmode = rm_dec.predmode
409 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
410 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
411
412 # elif predmode == CR:
413 # CR-src sidx, sinvert = get_predcr(m, srcpred)
414 # CR-dst didx, dinvert = get_predcr(m, dstpred)
415 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
416 # has to cope with first one then the other
417 # for cr_idx = FSM-state-loop(0..VL-1):
418 # FSM-state-trigger-CR-read:
419 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
420 # comb += cr_pred.ren.eq(cr_ren)
421 # FSM-state-1-clock-later-actual-Read:
422 # cr_field = Signal(4)
423 # cr_bit = Signal(1)
424 # # read the CR field, select the appropriate bit
425 # comb += cr_field.eq(cr_pred.data_o)
426 # comb += cr_bit.eq(cr_field.bit_select(idx)))
427 # # just like in branch BO tests
428 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
429
430 # decode predicates
431 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
432 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
433 sidx, scrinvert = get_predcr(m, srcpred, 's')
434 didx, dcrinvert = get_predcr(m, dstpred, 'd')
435
436 with m.FSM(name="fetch_predicate"):
437
438 with m.State("FETCH_PRED_IDLE"):
439 comb += pred_insn_ready_o.eq(1)
440 with m.If(pred_insn_valid_i):
441 with m.If(predmode == SVP64PredMode.INT):
442 # skip fetching destination mask register, when zero
443 with m.If(dall1s):
444 sync += self.dstmask.eq(-1)
445 # directly go to fetch source mask register
446 # guaranteed not to be zero (otherwise predmode
447 # would be SVP64PredMode.ALWAYS, not INT)
448 comb += int_pred.addr.eq(sregread)
449 comb += int_pred.ren.eq(1)
450 m.next = "INT_SRC_READ"
451 # fetch destination predicate register
452 with m.Else():
453 comb += int_pred.addr.eq(dregread)
454 comb += int_pred.ren.eq(1)
455 m.next = "INT_DST_READ"
456 with m.Else():
457 sync += self.srcmask.eq(-1)
458 sync += self.dstmask.eq(-1)
459 m.next = "FETCH_PRED_DONE"
460
461 with m.State("INT_DST_READ"):
462 # store destination mask
463 inv = Repl(dinvert, 64)
464 sync += self.dstmask.eq(self.int_pred.data_o ^ inv)
465 # skip fetching source mask register, when zero
466 with m.If(sall1s):
467 sync += self.srcmask.eq(-1)
468 m.next = "FETCH_PRED_DONE"
469 # fetch source predicate register
470 with m.Else():
471 comb += int_pred.addr.eq(sregread)
472 comb += int_pred.ren.eq(1)
473 m.next = "INT_SRC_READ"
474
475 with m.State("INT_SRC_READ"):
476 # store source mask
477 inv = Repl(sinvert, 64)
478 sync += self.srcmask.eq(self.int_pred.data_o ^ inv)
479 m.next = "FETCH_PRED_DONE"
480
481 with m.State("FETCH_PRED_DONE"):
482 comb += pred_mask_valid_o.eq(1)
483 with m.If(pred_mask_ready_i):
484 m.next = "FETCH_PRED_IDLE"
485
486 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
487 dbg, core_rst, is_svp64_mode,
488 fetch_pc_ready_o, fetch_pc_valid_i,
489 fetch_insn_valid_o, fetch_insn_ready_i,
490 pred_insn_valid_i, pred_insn_ready_o,
491 pred_mask_valid_o, pred_mask_ready_i,
492 exec_insn_valid_i, exec_insn_ready_o,
493 exec_pc_valid_o, exec_pc_ready_i):
494 """issue FSM
495
496 decode / issue FSM. this interacts with the "fetch" FSM
497 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
498 (outgoing). also interacts with the "execute" FSM
499 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
500 (incoming).
501 SVP64 RM prefixes have already been set up by the
502 "fetch" phase, so execute is fairly straightforward.
503 """
504
505 comb = m.d.comb
506 sync = m.d.sync
507 pdecode2 = self.pdecode2
508 cur_state = self.cur_state
509
510 # temporaries
511 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
512
513 # for updating svstate (things like srcstep etc.)
514 update_svstate = Signal() # set this (below) if updating
515 new_svstate = SVSTATERec("new_svstate")
516 comb += new_svstate.eq(cur_state.svstate)
517
518 # precalculate srcstep+1 and dststep+1
519 cur_srcstep = cur_state.svstate.srcstep
520 cur_dststep = cur_state.svstate.dststep
521 next_srcstep = Signal.like(cur_srcstep)
522 next_dststep = Signal.like(cur_dststep)
523 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
524 comb += next_dststep.eq(cur_state.svstate.dststep+1)
525
526 with m.FSM(name="issue_fsm"):
527
528 # sync with the "fetch" phase which is reading the instruction
529 # at this point, there is no instruction running, that
530 # could inadvertently update the PC.
531 with m.State("ISSUE_START"):
532 # wait on "core stop" release, before next fetch
533 # need to do this here, in case we are in a VL==0 loop
534 with m.If(~dbg.core_stop_o & ~core_rst):
535 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
536 with m.If(fetch_pc_ready_o): # fetch acknowledged us
537 m.next = "INSN_WAIT"
538 with m.Else():
539 # tell core it's stopped, and acknowledge debug handshake
540 comb += core.core_stopped_i.eq(1)
541 comb += dbg.core_stopped_i.eq(1)
542 # while stopped, allow updating the PC and SVSTATE
543 with m.If(self.pc_i.ok):
544 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
545 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
546 sync += pc_changed.eq(1)
547 with m.If(self.svstate_i.ok):
548 comb += new_svstate.eq(self.svstate_i.data)
549 comb += update_svstate.eq(1)
550 sync += sv_changed.eq(1)
551
552 # wait for an instruction to arrive from Fetch
553 with m.State("INSN_WAIT"):
554 comb += fetch_insn_ready_i.eq(1)
555 with m.If(fetch_insn_valid_o):
556 # loop into ISSUE_START if it's a SVP64 instruction
557 # and VL == 0. this because VL==0 is a for-loop
558 # from 0 to 0 i.e. always, always a NOP.
559 cur_vl = cur_state.svstate.vl
560 with m.If(is_svp64_mode & (cur_vl == 0)):
561 # update the PC before fetching the next instruction
562 # since we are in a VL==0 loop, no instruction was
563 # executed that we could be overwriting
564 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
565 comb += self.state_w_pc.data_i.eq(nia)
566 comb += self.insn_done.eq(1)
567 m.next = "ISSUE_START"
568 with m.Else():
569 if self.svp64_en:
570 m.next = "PRED_START" # start fetching predicate
571 else:
572 m.next = "DECODE_SV" # skip predication
573
574 with m.State("PRED_START"):
575 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
576 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
577 m.next = "MASK_WAIT"
578
579 with m.State("MASK_WAIT"):
580 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
581 with m.If(pred_mask_valid_o): # predication masks are ready
582 m.next = "PRED_SKIP"
583
584 # skip zeros in predicate
585 with m.State("PRED_SKIP"):
586 with m.If(~is_svp64_mode):
587 m.next = "DECODE_SV" # nothing to do
588 with m.Else():
589 if self.svp64_en:
590 pred_src_zero = pdecode2.rm_dec.pred_sz
591 pred_dst_zero = pdecode2.rm_dec.pred_dz
592
593 # new srcstep, after skipping zeros
594 skip_srcstep = Signal.like(cur_srcstep)
595 # value to be added to the current srcstep
596 src_delta = Signal.like(cur_srcstep)
597 # add leading zeros to srcstep, if not in zero mode
598 with m.If(~pred_src_zero):
599 # priority encoder (count leading zeros)
600 # append guard bit, in case the mask is all zeros
601 pri_enc_src = PriorityEncoder(65)
602 m.submodules.pri_enc_src = pri_enc_src
603 comb += pri_enc_src.i.eq(Cat(self.srcmask, 1))
604 comb += src_delta.eq(pri_enc_src.o)
605 # apply delta to srcstep
606 comb += skip_srcstep.eq(cur_srcstep + src_delta)
607 # shift-out all leading zeros from the mask
608 # plus the leading "one" bit
609 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
610
611 # same as above, but for dststep
612 skip_dststep = Signal.like(cur_dststep)
613 dst_delta = Signal.like(cur_dststep)
614 with m.If(~pred_dst_zero):
615 pri_enc_dst = PriorityEncoder(65)
616 m.submodules.pri_enc_dst = pri_enc_dst
617 comb += pri_enc_dst.i.eq(Cat(self.dstmask, 1))
618 comb += dst_delta.eq(pri_enc_dst.o)
619 comb += skip_dststep.eq(cur_dststep + dst_delta)
620 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
621
622 # TODO: initialize mask[VL]=1 to avoid passing past VL
623 with m.If((skip_srcstep >= cur_vl) |
624 (skip_dststep >= cur_vl)):
625 # end of VL loop. Update PC and reset src/dst step
626 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
627 comb += self.state_w_pc.data_i.eq(nia)
628 comb += new_svstate.srcstep.eq(0)
629 comb += new_svstate.dststep.eq(0)
630 comb += update_svstate.eq(1)
631 # go back to Issue
632 m.next = "ISSUE_START"
633 with m.Else():
634 # update new src/dst step
635 comb += new_svstate.srcstep.eq(skip_srcstep)
636 comb += new_svstate.dststep.eq(skip_dststep)
637 comb += update_svstate.eq(1)
638 # proceed to Decode
639 m.next = "DECODE_SV"
640
641 # after src/dst step have been updated, we are ready
642 # to decode the instruction
643 with m.State("DECODE_SV"):
644 # decode the instruction
645 sync += core.e.eq(pdecode2.e)
646 sync += core.state.eq(cur_state)
647 sync += core.raw_insn_i.eq(dec_opcode_i)
648 sync += core.bigendian_i.eq(self.core_bigendian_i)
649 # set RA_OR_ZERO detection in satellite decoders
650 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
651 m.next = "INSN_EXECUTE" # move to "execute"
652
653 # handshake with execution FSM, move to "wait" once acknowledged
654 with m.State("INSN_EXECUTE"):
655 comb += exec_insn_valid_i.eq(1) # trigger execute
656 with m.If(exec_insn_ready_o): # execute acknowledged us
657 m.next = "EXECUTE_WAIT"
658
659 with m.State("EXECUTE_WAIT"):
660 # wait on "core stop" release, at instruction end
661 # need to do this here, in case we are in a VL>1 loop
662 with m.If(~dbg.core_stop_o & ~core_rst):
663 comb += exec_pc_ready_i.eq(1)
664 with m.If(exec_pc_valid_o):
665
666 # was this the last loop iteration?
667 is_last = Signal()
668 cur_vl = cur_state.svstate.vl
669 comb += is_last.eq(next_srcstep == cur_vl)
670
671 # if either PC or SVSTATE were changed by the previous
672 # instruction, go directly back to Fetch, without
673 # updating either PC or SVSTATE
674 with m.If(pc_changed | sv_changed):
675 m.next = "ISSUE_START"
676
677 # also return to Fetch, when no output was a vector
678 # (regardless of SRCSTEP and VL), or when the last
679 # instruction was really the last one of the VL loop
680 with m.Elif((~pdecode2.loop_continue) | is_last):
681 # before going back to fetch, update the PC state
682 # register with the NIA.
683 # ok here we are not reading the branch unit.
684 # TODO: this just blithely overwrites whatever
685 # pipeline updated the PC
686 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
687 comb += self.state_w_pc.data_i.eq(nia)
688 # reset SRCSTEP before returning to Fetch
689 if self.svp64_en:
690 with m.If(pdecode2.loop_continue):
691 comb += new_svstate.srcstep.eq(0)
692 comb += new_svstate.dststep.eq(0)
693 comb += update_svstate.eq(1)
694 else:
695 comb += new_svstate.srcstep.eq(0)
696 comb += new_svstate.dststep.eq(0)
697 comb += update_svstate.eq(1)
698 m.next = "ISSUE_START"
699
700 # returning to Execute? then, first update SRCSTEP
701 with m.Else():
702 comb += new_svstate.srcstep.eq(next_srcstep)
703 comb += new_svstate.dststep.eq(next_dststep)
704 comb += update_svstate.eq(1)
705 # return to mask skip loop
706 m.next = "PRED_SKIP"
707
708 with m.Else():
709 comb += core.core_stopped_i.eq(1)
710 comb += dbg.core_stopped_i.eq(1)
711 # while stopped, allow updating the PC and SVSTATE
712 with m.If(self.pc_i.ok):
713 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
714 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
715 sync += pc_changed.eq(1)
716 with m.If(self.svstate_i.ok):
717 comb += new_svstate.eq(self.svstate_i.data)
718 comb += update_svstate.eq(1)
719 sync += sv_changed.eq(1)
720
721 # check if svstate needs updating: if so, write it to State Regfile
722 with m.If(update_svstate):
723 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
724 comb += self.state_w_sv.data_i.eq(new_svstate)
725 sync += cur_state.svstate.eq(new_svstate) # for next clock
726
727 def execute_fsm(self, m, core, pc_changed, sv_changed,
728 exec_insn_valid_i, exec_insn_ready_o,
729 exec_pc_valid_o, exec_pc_ready_i):
730 """execute FSM
731
732 execute FSM. this interacts with the "issue" FSM
733 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
734 (outgoing). SVP64 RM prefixes have already been set up by the
735 "issue" phase, so execute is fairly straightforward.
736 """
737
738 comb = m.d.comb
739 sync = m.d.sync
740 pdecode2 = self.pdecode2
741
742 # temporaries
743 core_busy_o = core.busy_o # core is busy
744 core_ivalid_i = core.ivalid_i # instruction is valid
745 core_issue_i = core.issue_i # instruction is issued
746 insn_type = core.e.do.insn_type # instruction MicroOp type
747
748 with m.FSM(name="exec_fsm"):
749
750 # waiting for instruction bus (stays there until not busy)
751 with m.State("INSN_START"):
752 comb += exec_insn_ready_o.eq(1)
753 with m.If(exec_insn_valid_i):
754 comb += core_ivalid_i.eq(1) # instruction is valid
755 comb += core_issue_i.eq(1) # and issued
756 sync += sv_changed.eq(0)
757 sync += pc_changed.eq(0)
758 m.next = "INSN_ACTIVE" # move to "wait completion"
759
760 # instruction started: must wait till it finishes
761 with m.State("INSN_ACTIVE"):
762 with m.If(insn_type != MicrOp.OP_NOP):
763 comb += core_ivalid_i.eq(1) # instruction is valid
764 # note changes to PC and SVSTATE
765 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
766 sync += sv_changed.eq(1)
767 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
768 sync += pc_changed.eq(1)
769 with m.If(~core_busy_o): # instruction done!
770 comb += exec_pc_valid_o.eq(1)
771 with m.If(exec_pc_ready_i):
772 comb += self.insn_done.eq(1)
773 m.next = "INSN_START" # back to fetch
774
775 def setup_peripherals(self, m):
776 comb, sync = m.d.comb, m.d.sync
777
778 m.submodules.core = core = DomainRenamer("coresync")(self.core)
779 m.submodules.imem = imem = self.imem
780 m.submodules.dbg = dbg = self.dbg
781 if self.jtag_en:
782 m.submodules.jtag = jtag = self.jtag
783 # TODO: UART2GDB mux, here, from external pin
784 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
785 sync += dbg.dmi.connect_to(jtag.dmi)
786
787 cur_state = self.cur_state
788
789 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
790 if self.sram4x4k:
791 for i, sram in enumerate(self.sram4k):
792 m.submodules["sram4k_%d" % i] = sram
793 comb += sram.enable.eq(self.wb_sram_en)
794
795 # XICS interrupt handler
796 if self.xics:
797 m.submodules.xics_icp = icp = self.xics_icp
798 m.submodules.xics_ics = ics = self.xics_ics
799 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
800 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
801
802 # GPIO test peripheral
803 if self.gpio:
804 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
805
806 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
807 # XXX causes litex ECP5 test to get wrong idea about input and output
808 # (but works with verilator sim *sigh*)
809 #if self.gpio and self.xics:
810 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
811
812 # instruction decoder
813 pdecode = create_pdecode()
814 m.submodules.dec2 = pdecode2 = self.pdecode2
815 if self.svp64_en:
816 m.submodules.svp64 = svp64 = self.svp64
817
818 # convenience
819 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
820 intrf = self.core.regs.rf['int']
821
822 # clock delay power-on reset
823 cd_por = ClockDomain(reset_less=True)
824 cd_sync = ClockDomain()
825 core_sync = ClockDomain("coresync")
826 m.domains += cd_por, cd_sync, core_sync
827
828 ti_rst = Signal(reset_less=True)
829 delay = Signal(range(4), reset=3)
830 with m.If(delay != 0):
831 m.d.por += delay.eq(delay - 1)
832 comb += cd_por.clk.eq(ClockSignal())
833
834 # power-on reset delay
835 core_rst = ResetSignal("coresync")
836 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
837 comb += core_rst.eq(ti_rst)
838
839 # busy/halted signals from core
840 comb += self.busy_o.eq(core.busy_o)
841 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
842
843 # temporary hack: says "go" immediately for both address gen and ST
844 l0 = core.l0
845 ldst = core.fus.fus['ldst0']
846 st_go_edge = rising_edge(m, ldst.st.rel_o)
847 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
848 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
849
850 return core_rst
851
852 def elaborate(self, platform):
853 m = Module()
854 # convenience
855 comb, sync = m.d.comb, m.d.sync
856 cur_state = self.cur_state
857 pdecode2 = self.pdecode2
858 dbg = self.dbg
859 core = self.core
860
861 # set up peripherals and core
862 core_rst = self.setup_peripherals(m)
863
864 # PC and instruction from I-Memory
865 comb += self.pc_o.eq(cur_state.pc)
866 pc_changed = Signal() # note write to PC
867 sv_changed = Signal() # note write to SVSTATE
868
869 # read state either from incoming override or from regfile
870 # TODO: really should be doing MSR in the same way
871 pc = state_get(m, self.pc_i, "pc", # read PC
872 self.state_r_pc, StateRegs.PC)
873 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
874 self.state_r_sv, StateRegs.SVSTATE)
875
876 # don't write pc every cycle
877 comb += self.state_w_pc.wen.eq(0)
878 comb += self.state_w_pc.data_i.eq(0)
879
880 # don't read msr every cycle
881 comb += self.state_r_msr.ren.eq(0)
882
883 # address of the next instruction, in the absence of a branch
884 # depends on the instruction size
885 nia = Signal(64, reset_less=True)
886
887 # connect up debug signals
888 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
889 comb += dbg.terminate_i.eq(core.core_terminate_o)
890 comb += dbg.state.pc.eq(pc)
891 comb += dbg.state.svstate.eq(svstate)
892 comb += dbg.state.msr.eq(cur_state.msr)
893
894 # pass the prefix mode from Fetch to Issue, so the latter can loop
895 # on VL==0
896 is_svp64_mode = Signal()
897
898 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
899 # these are the handshake signals between fetch and decode/execute
900
901 # fetch FSM can run as soon as the PC is valid
902 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
903 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
904
905 # fetch FSM hands over the instruction to be decoded / issued
906 fetch_insn_valid_o = Signal()
907 fetch_insn_ready_i = Signal()
908
909 # predicate fetch FSM decodes and fetches the predicate
910 pred_insn_valid_i = Signal()
911 pred_insn_ready_o = Signal()
912
913 # predicate fetch FSM delivers the masks
914 pred_mask_valid_o = Signal()
915 pred_mask_ready_i = Signal()
916
917 # issue FSM delivers the instruction to the be executed
918 exec_insn_valid_i = Signal()
919 exec_insn_ready_o = Signal()
920
921 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
922 exec_pc_valid_o = Signal()
923 exec_pc_ready_i = Signal()
924
925 # the FSMs here are perhaps unusual in that they detect conditions
926 # then "hold" information, combinatorially, for the core
927 # (as opposed to using sync - which would be on a clock's delay)
928 # this includes the actual opcode, valid flags and so on.
929
930 # Fetch, then predicate fetch, then Issue, then Execute.
931 # Issue is where the VL for-loop # lives. the ready/valid
932 # signalling is used to communicate between the four.
933
934 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
935 fetch_pc_ready_o, fetch_pc_valid_i,
936 fetch_insn_valid_o, fetch_insn_ready_i)
937
938 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
939 dbg, core_rst, is_svp64_mode,
940 fetch_pc_ready_o, fetch_pc_valid_i,
941 fetch_insn_valid_o, fetch_insn_ready_i,
942 pred_insn_valid_i, pred_insn_ready_o,
943 pred_mask_valid_o, pred_mask_ready_i,
944 exec_insn_valid_i, exec_insn_ready_o,
945 exec_pc_valid_o, exec_pc_ready_i)
946
947 if self.svp64_en:
948 self.fetch_predicate_fsm(m,
949 pred_insn_valid_i, pred_insn_ready_o,
950 pred_mask_valid_o, pred_mask_ready_i)
951
952 self.execute_fsm(m, core, pc_changed, sv_changed,
953 exec_insn_valid_i, exec_insn_ready_o,
954 exec_pc_valid_o, exec_pc_ready_i)
955
956 # this bit doesn't have to be in the FSM: connect up to read
957 # regfiles on demand from DMI
958 self.do_dmi(m, dbg)
959
960 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
961 # (which uses that in PowerDecoder2 to raise 0x900 exception)
962 self.tb_dec_fsm(m, cur_state.dec)
963
964 return m
965
966 def do_dmi(self, m, dbg):
967 """deals with DMI debug requests
968
969 currently only provides read requests for the INT regfile, CR and XER
970 it will later also deal with *writing* to these regfiles.
971 """
972 comb = m.d.comb
973 sync = m.d.sync
974 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
975 intrf = self.core.regs.rf['int']
976
977 with m.If(d_reg.req): # request for regfile access being made
978 # TODO: error-check this
979 # XXX should this be combinatorial? sync better?
980 if intrf.unary:
981 comb += self.int_r.ren.eq(1<<d_reg.addr)
982 else:
983 comb += self.int_r.addr.eq(d_reg.addr)
984 comb += self.int_r.ren.eq(1)
985 d_reg_delay = Signal()
986 sync += d_reg_delay.eq(d_reg.req)
987 with m.If(d_reg_delay):
988 # data arrives one clock later
989 comb += d_reg.data.eq(self.int_r.data_o)
990 comb += d_reg.ack.eq(1)
991
992 # sigh same thing for CR debug
993 with m.If(d_cr.req): # request for regfile access being made
994 comb += self.cr_r.ren.eq(0b11111111) # enable all
995 d_cr_delay = Signal()
996 sync += d_cr_delay.eq(d_cr.req)
997 with m.If(d_cr_delay):
998 # data arrives one clock later
999 comb += d_cr.data.eq(self.cr_r.data_o)
1000 comb += d_cr.ack.eq(1)
1001
1002 # aaand XER...
1003 with m.If(d_xer.req): # request for regfile access being made
1004 comb += self.xer_r.ren.eq(0b111111) # enable all
1005 d_xer_delay = Signal()
1006 sync += d_xer_delay.eq(d_xer.req)
1007 with m.If(d_xer_delay):
1008 # data arrives one clock later
1009 comb += d_xer.data.eq(self.xer_r.data_o)
1010 comb += d_xer.ack.eq(1)
1011
1012 def tb_dec_fsm(self, m, spr_dec):
1013 """tb_dec_fsm
1014
1015 this is a FSM for updating either dec or tb. it runs alternately
1016 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1017 value to DEC, however the regfile has "passthrough" on it so this
1018 *should* be ok.
1019
1020 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1021 """
1022
1023 comb, sync = m.d.comb, m.d.sync
1024 fast_rf = self.core.regs.rf['fast']
1025 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1026 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1027
1028 with m.FSM() as fsm:
1029
1030 # initiates read of current DEC
1031 with m.State("DEC_READ"):
1032 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1033 comb += fast_r_dectb.ren.eq(1)
1034 m.next = "DEC_WRITE"
1035
1036 # waits for DEC read to arrive (1 cycle), updates with new value
1037 with m.State("DEC_WRITE"):
1038 new_dec = Signal(64)
1039 # TODO: MSR.LPCR 32-bit decrement mode
1040 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1041 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1042 comb += fast_w_dectb.wen.eq(1)
1043 comb += fast_w_dectb.data_i.eq(new_dec)
1044 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1045 m.next = "TB_READ"
1046
1047 # initiates read of current TB
1048 with m.State("TB_READ"):
1049 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1050 comb += fast_r_dectb.ren.eq(1)
1051 m.next = "TB_WRITE"
1052
1053 # waits for read TB to arrive, initiates write of current TB
1054 with m.State("TB_WRITE"):
1055 new_tb = Signal(64)
1056 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1057 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1058 comb += fast_w_dectb.wen.eq(1)
1059 comb += fast_w_dectb.data_i.eq(new_tb)
1060 m.next = "DEC_READ"
1061
1062 return m
1063
1064 def __iter__(self):
1065 yield from self.pc_i.ports()
1066 yield self.pc_o
1067 yield self.memerr_o
1068 yield from self.core.ports()
1069 yield from self.imem.ports()
1070 yield self.core_bigendian_i
1071 yield self.busy_o
1072
1073 def ports(self):
1074 return list(self)
1075
1076 def external_ports(self):
1077 ports = self.pc_i.ports()
1078 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1079 ]
1080
1081 if self.jtag_en:
1082 ports += list(self.jtag.external_ports())
1083 else:
1084 # don't add DMI if JTAG is enabled
1085 ports += list(self.dbg.dmi.ports())
1086
1087 ports += list(self.imem.ibus.fields.values())
1088 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1089
1090 if self.sram4x4k:
1091 for sram in self.sram4k:
1092 ports += list(sram.bus.fields.values())
1093
1094 if self.xics:
1095 ports += list(self.xics_icp.bus.fields.values())
1096 ports += list(self.xics_ics.bus.fields.values())
1097 ports.append(self.int_level_i)
1098
1099 if self.gpio:
1100 ports += list(self.simple_gpio.bus.fields.values())
1101 ports.append(self.gpio_o)
1102
1103 return ports
1104
1105 def ports(self):
1106 return list(self)
1107
1108
1109 class TestIssuer(Elaboratable):
1110 def __init__(self, pspec):
1111 self.ti = TestIssuerInternal(pspec)
1112
1113 self.pll = DummyPLL()
1114
1115 # PLL direct clock or not
1116 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1117 if self.pll_en:
1118 self.pll_18_o = Signal(reset_less=True)
1119
1120 def elaborate(self, platform):
1121 m = Module()
1122 comb = m.d.comb
1123
1124 # TestIssuer runs at direct clock
1125 m.submodules.ti = ti = self.ti
1126 cd_int = ClockDomain("coresync")
1127
1128 if self.pll_en:
1129 # ClockSelect runs at PLL output internal clock rate
1130 m.submodules.pll = pll = self.pll
1131
1132 # add clock domains from PLL
1133 cd_pll = ClockDomain("pllclk")
1134 m.domains += cd_pll
1135
1136 # PLL clock established. has the side-effect of running clklsel
1137 # at the PLL's speed (see DomainRenamer("pllclk") above)
1138 pllclk = ClockSignal("pllclk")
1139 comb += pllclk.eq(pll.clk_pll_o)
1140
1141 # wire up external 24mhz to PLL
1142 comb += pll.clk_24_i.eq(ClockSignal())
1143
1144 # output 18 mhz PLL test signal
1145 comb += self.pll_18_o.eq(pll.pll_18_o)
1146
1147 # now wire up ResetSignals. don't mind them being in this domain
1148 pll_rst = ResetSignal("pllclk")
1149 comb += pll_rst.eq(ResetSignal())
1150
1151 # internal clock is set to selector clock-out. has the side-effect of
1152 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1153 intclk = ClockSignal("coresync")
1154 if self.pll_en:
1155 comb += intclk.eq(pll.clk_pll_o)
1156 else:
1157 comb += intclk.eq(ClockSignal())
1158
1159 return m
1160
1161 def ports(self):
1162 return list(self.ti.ports()) + list(self.pll.ports()) + \
1163 [ClockSignal(), ResetSignal()]
1164
1165 def external_ports(self):
1166 ports = self.ti.external_ports()
1167 ports.append(ClockSignal())
1168 ports.append(ResetSignal())
1169 if self.pll_en:
1170 ports.append(self.pll.clk_sel_i)
1171 ports.append(self.pll_18_o)
1172 ports.append(self.pll.pll_lck_o)
1173 return ports
1174
1175
1176 if __name__ == '__main__':
1177 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1178 'spr': 1,
1179 'div': 1,
1180 'mul': 1,
1181 'shiftrot': 1
1182 }
1183 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1184 imem_ifacetype='bare_wb',
1185 addr_wid=48,
1186 mask_wid=8,
1187 reg_wid=64,
1188 units=units)
1189 dut = TestIssuer(pspec)
1190 vl = main(dut, ports=dut.ports(), name="test_issuer")
1191
1192 if len(sys.argv) == 1:
1193 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1194 with open("test_issuer.il", "w") as f:
1195 f.write(vl)