src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55 # gets state input or reads from state regfile
  56 def state_get(m, state_i, name, regfile, regnum):
  57     comb = m.d.comb
  58     sync = m.d.sync
  59     # read the PC
  60     res = Signal(64, reset_less=True, name=name)
  61     res_ok_delay = Signal(name="%s_ok_delay" % name)
  62     sync += res_ok_delay.eq(~state_i.ok)
  63     with m.If(state_i.ok):
  64         # incoming override (start from pc_i)
  65         comb += res.eq(state_i.data)
  66     with m.Else():
  67         # otherwise read StateRegs regfile for PC...
  68         comb += regfile.ren.eq(1<<regnum)
  69     # ... but on a 1-clock delay
  70     with m.If(res_ok_delay):
  71         comb += res.eq(regfile.data_o)
  72     return res
  73
  74 def get_predint(m, mask):
  75     """decode SVP64 predicate integer mask field to reg number and invert
  76     """
  77     regread = Signal(5)
  78     invert = Signal()
  79     unary = Signal()
  80     with m.Switch(mask):
  81         with m.Case(SVP64PredInt.ALWAYS.value):
  82             comb += regread.eq(0)
  83             comb += invert.eq(1)
  84         with m.Case(SVP64PredInt.R3_UNARY.value):
  85             comb += regread.eq(3)
  86             comb += unary.eq(1)
  87         with m.Case(SVP64PredInt.R3.value):
  88             comb += regread.eq(3)
  89         with m.Case(SVP64PredInt.R3_N.value):
  90             comb += regread.eq(3)
  91             comb += invert.eq(1)
  92         with m.Case(SVP64PredInt.R10.value):
  93             comb += regread.eq(10)
  94         with m.Case(SVP64PredInt.R10_N.value):
  95             comb += regread.eq(10)
  96             comb += invert.eq(1)
  97         with m.Case(SVP64PredInt.R30.value):
  98             comb += regread.eq(30)
  99         with m.Case(SVP64PredInt.R30_N.value):
 100             comb += regread.eq(30)
 101             comb += invert.eq(1)
 102     return regread, invert, unary
 103
 104 def get_predcr(m, mask):
 105     """decode SVP64 predicate CR to reg number field and invert status
 106     """
 107     idx = Signal(2)
 108     invert = Signal()
 109     with m.Switch(mask):
 110         with m.Case(SVP64PredCR.LT.value):
 111             comb += idx.eq(0)
 112             comb += invert.eq(1)
 113         with m.Case(SVP64PredCR.GE.value):
 114             comb += idx.eq(0)
 115             comb += invert.eq(0)
 116         with m.Case(SVP64PredCR.GT.value):
 117             comb += idx.eq(1)
 118             comb += invert.eq(1)
 119         with m.Case(SVP64PredCR.LE.value):
 120             comb += idx.eq(1)
 121             comb += invert.eq(0)
 122         with m.Case(SVP64PredCR.EQ.value):
 123             comb += idx.eq(2)
 124             comb += invert.eq(1)
 125         with m.Case(SVP64PredCR.NE.value):
 126             comb += idx.eq(1)
 127             comb += invert.eq(0)
 128         with m.Case(SVP64PredCR.SO.value):
 129             comb += idx.eq(3)
 130             comb += invert.eq(1)
 131         with m.Case(SVP64PredCR.NS.value):
 132             comb += idx.eq(3)
 133             comb += invert.eq(0)
 134     return idx, invert
 135
 136
 137 class TestIssuerInternal(Elaboratable):
 138     """TestIssuer - reads instructions from TestMemory and issues them
 139
 140     efficiency and speed is not the main goal here: functional correctness is.
 141     """
 142     def __init__(self, pspec):
 143
 144         # test is SVP64 is to be enabled
 145         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 146
 147         # JTAG interface.  add this right at the start because if it's
 148         # added it *modifies* the pspec, by adding enable/disable signals
 149         # for parts of the rest of the core
 150         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
 151         if self.jtag_en:
 152             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 153                       'pwm', 'sd0', 'sdr'}
 154             self.jtag = JTAG(get_pinspecs(subset=subset))
 155             # add signals to pspec to enable/disable icache and dcache
 156             # (or data and intstruction wishbone if icache/dcache not included)
 157             # https://bugs.libre-soc.org/show_bug.cgi?id=520
 158             # TODO: do we actually care if these are not domain-synchronised?
 159             # honestly probably not.
 160             pspec.wb_icache_en = self.jtag.wb_icache_en
 161             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 162             self.wb_sram_en = self.jtag.wb_sram_en
 163         else:
 164             self.wb_sram_en = Const(1)
 165
 166         # add 4k sram blocks?
 167         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
 168                          pspec.sram4x4kblock == True)
 169         if self.sram4x4k:
 170             self.sram4k = []
 171             for i in range(4):
 172                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
 173                                                     features={'err'}))
 174
 175         # add interrupt controller?
 176         self.xics = hasattr(pspec, "xics") and pspec.xics == True
 177         if self.xics:
 178             self.xics_icp = XICS_ICP()
 179             self.xics_ics = XICS_ICS()
 180             self.int_level_i = self.xics_ics.int_level_i
 181
 182         # add GPIO peripheral?
 183         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 184         if self.gpio:
 185             self.simple_gpio = SimpleGPIO()
 186             self.gpio_o = self.simple_gpio.gpio_o
 187
 188         # main instruction core.  suitable for prototyping / demo only
 189         self.core = core = NonProductionCore(pspec)
 190
 191         # instruction decoder.  goes into Trap Record
 192         pdecode = create_pdecode()
 193         self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
 194         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 195                                      opkls=IssuerDecode2ToOperand,
 196                                      svp64_en=self.svp64_en)
 197         if self.svp64_en:
 198             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 199
 200         # Test Instruction memory
 201         self.imem = ConfigFetchUnit(pspec).fu
 202
 203         # DMI interface
 204         self.dbg = CoreDebug()
 205
 206         # instruction go/monitor
 207         self.pc_o = Signal(64, reset_less=True)
 208         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 209         self.svstate_i = Data(32, "svstate_i") # ditto
 210         self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
 211         self.busy_o = Signal(reset_less=True)
 212         self.memerr_o = Signal(reset_less=True)
 213
 214         # STATE regfile read /write ports for PC, MSR, SVSTATE
 215         staterf = self.core.regs.rf['state']
 216         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 217         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 218         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 219         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 220         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 221
 222         # DMI interface access
 223         intrf = self.core.regs.rf['int']
 224         crrf = self.core.regs.rf['cr']
 225         xerrf = self.core.regs.rf['xer']
 226         self.int_r = intrf.r_ports['dmi'] # INT read
 227         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 228         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 229
 230         # for predication
 231         self.int_pred = intrf.r_ports['pred'] # INT predicate read
 232         self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
 233
 234         # hack method of keeping an eye on whether branch/trap set the PC
 235         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 236         self.state_nia.wen.name = 'state_nia_wen'
 237
 238         # pulse to synchronize the simulator at instruction end
 239         self.insn_done = Signal()
 240
 241         if self.svp64_en:
 242             # store copies of predicate masks
 243             self.srcmask = Signal(64)
 244             self.dstmask = Signal(64)
 245
 246     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 247                         fetch_pc_ready_o, fetch_pc_valid_i,
 248                         fetch_insn_valid_o, fetch_insn_ready_i):
 249         """fetch FSM
 250         this FSM performs fetch of raw instruction data, partial-decodes
 251         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 252         read a 2nd 32-bit quantity if that occurs.
 253         """
 254         comb = m.d.comb
 255         sync = m.d.sync
 256         pdecode2 = self.pdecode2
 257         cur_state = self.cur_state
 258         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 259
 260         msr_read = Signal(reset=1)
 261
 262         with m.FSM(name='fetch_fsm'):
 263
 264             # waiting (zzz)
 265             with m.State("IDLE"):
 266                 comb += fetch_pc_ready_o.eq(1)
 267                 with m.If(fetch_pc_valid_i):
 268                     # instruction allowed to go: start by reading the PC
 269                     # capture the PC and also drop it into Insn Memory
 270                     # we have joined a pair of combinatorial memory
 271                     # lookups together.  this is Generally Bad.
 272                     comb += self.imem.a_pc_i.eq(pc)
 273                     comb += self.imem.a_valid_i.eq(1)
 274                     comb += self.imem.f_valid_i.eq(1)
 275                     sync += cur_state.pc.eq(pc)
 276                     sync += cur_state.svstate.eq(svstate) # and svstate
 277
 278                     # initiate read of MSR. arrives one clock later
 279                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 280                     sync += msr_read.eq(0)
 281
 282                     m.next = "INSN_READ"  # move to "wait for bus" phase
 283
 284             # dummy pause to find out why simulation is not keeping up
 285             with m.State("INSN_READ"):
 286                 # one cycle later, msr/sv read arrives.  valid only once.
 287                 with m.If(~msr_read):
 288                     sync += msr_read.eq(1) # yeah don't read it again
 289                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 290                 with m.If(self.imem.f_busy_o): # zzz...
 291                     # busy: stay in wait-read
 292                     comb += self.imem.a_valid_i.eq(1)
 293                     comb += self.imem.f_valid_i.eq(1)
 294                 with m.Else():
 295                     # not busy: instruction fetched
 296                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 297                     if self.svp64_en:
 298                         svp64 = self.svp64
 299                         # decode the SVP64 prefix, if any
 300                         comb += svp64.raw_opcode_in.eq(insn)
 301                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 302                         # pass the decoded prefix (if any) to PowerDecoder2
 303                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 304                         # remember whether this is a prefixed instruction, so
 305                         # the FSM can readily loop when VL==0
 306                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 307                         # calculate the address of the following instruction
 308                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 309                         sync += nia.eq(cur_state.pc + insn_size)
 310                         with m.If(~svp64.is_svp64_mode):
 311                             # with no prefix, store the instruction
 312                             # and hand it directly to the next FSM
 313                             sync += dec_opcode_i.eq(insn)
 314                             m.next = "INSN_READY"
 315                         with m.Else():
 316                             # fetch the rest of the instruction from memory
 317                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 318                             comb += self.imem.a_valid_i.eq(1)
 319                             comb += self.imem.f_valid_i.eq(1)
 320                             m.next = "INSN_READ2"
 321                     else:
 322                         # not SVP64 - 32-bit only
 323                         sync += nia.eq(cur_state.pc + 4)
 324                         sync += dec_opcode_i.eq(insn)
 325                         m.next = "INSN_READY"
 326
 327             with m.State("INSN_READ2"):
 328                 with m.If(self.imem.f_busy_o):  # zzz...
 329                     # busy: stay in wait-read
 330                     comb += self.imem.a_valid_i.eq(1)
 331                     comb += self.imem.f_valid_i.eq(1)
 332                 with m.Else():
 333                     # not busy: instruction fetched
 334                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 335                     sync += dec_opcode_i.eq(insn)
 336                     m.next = "INSN_READY"
 337                     # TODO: probably can start looking at pdecode2.rm_dec
 338                     # here (or maybe even in INSN_READ state, if svp64_mode
 339                     # detected, in order to trigger - and wait for - the
 340                     # predicate reading.
 341
 342             with m.State("INSN_READY"):
 343                 # hand over the instruction, to be decoded
 344                 comb += fetch_insn_valid_o.eq(1)
 345                 with m.If(fetch_insn_ready_i):
 346                     m.next = "IDLE"
 347
 348     def fetch_predicate_fsm(self, m, core, TODO):
 349         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 350            src/dest predicate masks
 351
 352         https://bugs.libre-soc.org/show_bug.cgi?id=617
 353         the predicates can be read here, by using IntRegs r_ports['pred']
 354         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 355         be done through multiple reads, extracting one relevant at a time.
 356         later, a faster way would be to use the 32-bit-wide CR port but
 357         this is more complex decoding, here.  equivalent code used in
 358         ISACaller is "from soc.decoder.isa.caller import get_predcr"
 359         """
 360         comb = m.d.comb
 361         sync = m.d.sync
 362         pdecode2 = self.pdecode2
 363         rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
 364         predmode = rm_dec.predmode
 365         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 366         cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
 367         # if predmode == INT:
 368         #    INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
 369         #    INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
 370         #    TODO read INT-src and INT-dst into self.srcmask+dstmask
 371         # elif predmode == CR:
 372         #    CR-src sidx, sinvert = get_predcr(m, srcpred)
 373         #    CR-dst didx, dinvert = get_predcr(m, dstpred)
 374         #    TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
 375         # else
 376         #    sync += self.srcmask.eq(-1) # set to all 1s
 377         #    sync += self.dstmask.eq(-1) # set to all 1s
 378
 379     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 380                   dbg, core_rst, is_svp64_mode,
 381                   fetch_pc_ready_o, fetch_pc_valid_i,
 382                   fetch_insn_valid_o, fetch_insn_ready_i,
 383                   exec_insn_valid_i, exec_insn_ready_o,
 384                   exec_pc_valid_o, exec_pc_ready_i):
 385         """issue FSM
 386
 387         decode / issue FSM.  this interacts with the "fetch" FSM
 388         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 389         (outgoing). also interacts with the "execute" FSM
 390         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 391         (incoming).
 392         SVP64 RM prefixes have already been set up by the
 393         "fetch" phase, so execute is fairly straightforward.
 394         """
 395
 396         comb = m.d.comb
 397         sync = m.d.sync
 398         pdecode2 = self.pdecode2
 399         cur_state = self.cur_state
 400
 401         # temporaries
 402         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 403
 404         # for updating svstate (things like srcstep etc.)
 405         update_svstate = Signal() # set this (below) if updating
 406         new_svstate = SVSTATERec("new_svstate")
 407         comb += new_svstate.eq(cur_state.svstate)
 408
 409         with m.FSM(name="issue_fsm"):
 410
 411             # sync with the "fetch" phase which is reading the instruction
 412             # at this point, there is no instruction running, that
 413             # could inadvertently update the PC.
 414             with m.State("ISSUE_START"):
 415                 # wait on "core stop" release, before next fetch
 416                 # need to do this here, in case we are in a VL==0 loop
 417                 with m.If(~dbg.core_stop_o & ~core_rst):
 418                     comb += fetch_pc_valid_i.eq(1) # tell fetch to start
 419                     with m.If(fetch_pc_ready_o):   # fetch acknowledged us
 420                         m.next = "INSN_WAIT"
 421                 with m.Else():
 422                     # tell core it's stopped, and acknowledge debug handshake
 423                     comb += core.core_stopped_i.eq(1)
 424                     comb += dbg.core_stopped_i.eq(1)
 425                     # while stopped, allow updating the PC and SVSTATE
 426                     with m.If(self.pc_i.ok):
 427                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 428                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 429                         sync += pc_changed.eq(1)
 430                     with m.If(self.svstate_i.ok):
 431                         comb += new_svstate.eq(self.svstate_i.data)
 432                         comb += update_svstate.eq(1)
 433                         sync += sv_changed.eq(1)
 434
 435             # decode the instruction when it arrives
 436             with m.State("INSN_WAIT"):
 437                 comb += fetch_insn_ready_i.eq(1)
 438                 with m.If(fetch_insn_valid_o):
 439                     # decode the instruction
 440                     sync += core.e.eq(pdecode2.e)
 441                     sync += core.state.eq(cur_state)
 442                     sync += core.raw_insn_i.eq(dec_opcode_i)
 443                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 444                     # set RA_OR_ZERO detection in satellite decoders
 445                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 446                     # loop into ISSUE_START if it's a SVP64 instruction
 447                     # and VL == 0.  this because VL==0 is a for-loop
 448                     # from 0 to 0 i.e. always, always a NOP.
 449                     cur_vl = cur_state.svstate.vl
 450                     with m.If(is_svp64_mode & (cur_vl == 0)):
 451                         # update the PC before fetching the next instruction
 452                         # since we are in a VL==0 loop, no instruction was
 453                         # executed that we could be overwriting
 454                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 455                         comb += self.state_w_pc.data_i.eq(nia)
 456                         comb += self.insn_done.eq(1)
 457                         m.next = "ISSUE_START"
 458                     with m.Else():
 459                         m.next = "INSN_EXECUTE"  # move to "execute"
 460
 461             # handshake with execution FSM, move to "wait" once acknowledged
 462             with m.State("INSN_EXECUTE"):
 463                 # with m.If(is_svp64_mode):
 464                 #    TODO advance src/dst step to "skip" over predicated-out
 465                 #    from self.srcmask and self.dstmask
 466                 #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
 467                 #    but still without exceeding VL in either case
 468                 comb += exec_insn_valid_i.eq(1) # trigger execute
 469                 with m.If(exec_insn_ready_o):   # execute acknowledged us
 470                     m.next = "EXECUTE_WAIT"
 471
 472             with m.State("EXECUTE_WAIT"):
 473                 # wait on "core stop" release, at instruction end
 474                 # need to do this here, in case we are in a VL>1 loop
 475                 with m.If(~dbg.core_stop_o & ~core_rst):
 476                     comb += exec_pc_ready_i.eq(1)
 477                     with m.If(exec_pc_valid_o):
 478                         # precalculate srcstep+1 and dststep+1
 479                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 480                         next_dststep = Signal.like(cur_state.svstate.dststep)
 481                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 482                         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 483
 484                         # was this the last loop iteration?
 485                         is_last = Signal()
 486                         cur_vl = cur_state.svstate.vl
 487                         comb += is_last.eq(next_srcstep == cur_vl)
 488
 489                         # if either PC or SVSTATE were changed by the previous
 490                         # instruction, go directly back to Fetch, without
 491                         # updating either PC or SVSTATE
 492                         with m.If(pc_changed | sv_changed):
 493                             m.next = "ISSUE_START"
 494
 495                         # also return to Fetch, when no output was a vector
 496                         # (regardless of SRCSTEP and VL), or when the last
 497                         # instruction was really the last one of the VL loop
 498                         with m.Elif((~pdecode2.loop_continue) | is_last):
 499                             # before going back to fetch, update the PC state
 500                             # register with the NIA.
 501                             # ok here we are not reading the branch unit.
 502                             # TODO: this just blithely overwrites whatever
 503                             #       pipeline updated the PC
 504                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 505                             comb += self.state_w_pc.data_i.eq(nia)
 506                             # reset SRCSTEP before returning to Fetch
 507                             with m.If(pdecode2.loop_continue):
 508                                 comb += new_svstate.srcstep.eq(0)
 509                                 comb += new_svstate.dststep.eq(0)
 510                                 comb += update_svstate.eq(1)
 511                             m.next = "ISSUE_START"
 512
 513                         # returning to Execute? then, first update SRCSTEP
 514                         with m.Else():
 515                             comb += new_svstate.srcstep.eq(next_srcstep)
 516                             comb += new_svstate.dststep.eq(next_dststep)
 517                             comb += update_svstate.eq(1)
 518                             m.next = "DECODE_SV"
 519
 520                 with m.Else():
 521                     comb += core.core_stopped_i.eq(1)
 522                     comb += dbg.core_stopped_i.eq(1)
 523                     # while stopped, allow updating the PC and SVSTATE
 524                     with m.If(self.pc_i.ok):
 525                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 526                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 527                         sync += pc_changed.eq(1)
 528                     with m.If(self.svstate_i.ok):
 529                         comb += new_svstate.eq(self.svstate_i.data)
 530                         comb += update_svstate.eq(1)
 531                         sync += sv_changed.eq(1)
 532
 533             # need to decode the instruction again, after updating SRCSTEP
 534             # in the previous state.
 535             # mostly a copy of INSN_WAIT, but without the actual wait
 536             with m.State("DECODE_SV"):
 537                 # decode the instruction
 538                 sync += core.e.eq(pdecode2.e)
 539                 sync += core.state.eq(cur_state)
 540                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 541                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 542                 m.next = "INSN_EXECUTE"  # move to "execute"
 543
 544         # check if svstate needs updating: if so, write it to State Regfile
 545         with m.If(update_svstate):
 546             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 547             comb += self.state_w_sv.data_i.eq(new_svstate)
 548             sync += cur_state.svstate.eq(new_svstate) # for next clock
 549
 550     def execute_fsm(self, m, core, pc_changed, sv_changed,
 551                     exec_insn_valid_i, exec_insn_ready_o,
 552                     exec_pc_valid_o, exec_pc_ready_i):
 553         """execute FSM
 554
 555         execute FSM. this interacts with the "issue" FSM
 556         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 557         (outgoing). SVP64 RM prefixes have already been set up by the
 558         "issue" phase, so execute is fairly straightforward.
 559         """
 560
 561         comb = m.d.comb
 562         sync = m.d.sync
 563         pdecode2 = self.pdecode2
 564
 565         # temporaries
 566         core_busy_o = core.busy_o                 # core is busy
 567         core_ivalid_i = core.ivalid_i             # instruction is valid
 568         core_issue_i = core.issue_i               # instruction is issued
 569         insn_type = core.e.do.insn_type           # instruction MicroOp type
 570
 571         with m.FSM(name="exec_fsm"):
 572
 573             # waiting for instruction bus (stays there until not busy)
 574             with m.State("INSN_START"):
 575                 comb += exec_insn_ready_o.eq(1)
 576                 with m.If(exec_insn_valid_i):
 577                     comb += core_ivalid_i.eq(1)  # instruction is valid
 578                     comb += core_issue_i.eq(1)  # and issued
 579                     sync += sv_changed.eq(0)
 580                     sync += pc_changed.eq(0)
 581                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 582
 583             # instruction started: must wait till it finishes
 584             with m.State("INSN_ACTIVE"):
 585                 with m.If(insn_type != MicrOp.OP_NOP):
 586                     comb += core_ivalid_i.eq(1) # instruction is valid
 587                 # note changes to PC and SVSTATE
 588                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 589                     sync += sv_changed.eq(1)
 590                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 591                     sync += pc_changed.eq(1)
 592                 with m.If(~core_busy_o): # instruction done!
 593                     comb += exec_pc_valid_o.eq(1)
 594                     with m.If(exec_pc_ready_i):
 595                         comb += self.insn_done.eq(1)
 596                         m.next = "INSN_START"  # back to fetch
 597
 598     def setup_peripherals(self, m):
 599         comb, sync = m.d.comb, m.d.sync
 600
 601         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 602         m.submodules.imem = imem = self.imem
 603         m.submodules.dbg = dbg = self.dbg
 604         if self.jtag_en:
 605             m.submodules.jtag = jtag = self.jtag
 606             # TODO: UART2GDB mux, here, from external pin
 607             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 608             sync += dbg.dmi.connect_to(jtag.dmi)
 609
 610         cur_state = self.cur_state
 611
 612         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 613         if self.sram4x4k:
 614             for i, sram in enumerate(self.sram4k):
 615                 m.submodules["sram4k_%d" % i] = sram
 616                 comb += sram.enable.eq(self.wb_sram_en)
 617
 618         # XICS interrupt handler
 619         if self.xics:
 620             m.submodules.xics_icp = icp = self.xics_icp
 621             m.submodules.xics_ics = ics = self.xics_ics
 622             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 623             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 624
 625         # GPIO test peripheral
 626         if self.gpio:
 627             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 628
 629         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 630         # XXX causes litex ECP5 test to get wrong idea about input and output
 631         # (but works with verilator sim *sigh*)
 632         #if self.gpio and self.xics:
 633         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 634
 635         # instruction decoder
 636         pdecode = create_pdecode()
 637         m.submodules.dec2 = pdecode2 = self.pdecode2
 638         if self.svp64_en:
 639             m.submodules.svp64 = svp64 = self.svp64
 640
 641         # convenience
 642         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 643         intrf = self.core.regs.rf['int']
 644
 645         # clock delay power-on reset
 646         cd_por  = ClockDomain(reset_less=True)
 647         cd_sync = ClockDomain()
 648         core_sync = ClockDomain("coresync")
 649         m.domains += cd_por, cd_sync, core_sync
 650
 651         ti_rst = Signal(reset_less=True)
 652         delay = Signal(range(4), reset=3)
 653         with m.If(delay != 0):
 654             m.d.por += delay.eq(delay - 1)
 655         comb += cd_por.clk.eq(ClockSignal())
 656
 657         # power-on reset delay
 658         core_rst = ResetSignal("coresync")
 659         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 660         comb += core_rst.eq(ti_rst)
 661
 662         # busy/halted signals from core
 663         comb += self.busy_o.eq(core.busy_o)
 664         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 665
 666         # temporary hack: says "go" immediately for both address gen and ST
 667         l0 = core.l0
 668         ldst = core.fus.fus['ldst0']
 669         st_go_edge = rising_edge(m, ldst.st.rel_o)
 670         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 671         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 672
 673         return core_rst
 674
 675     def elaborate(self, platform):
 676         m = Module()
 677         # convenience
 678         comb, sync = m.d.comb, m.d.sync
 679         cur_state = self.cur_state
 680         pdecode2 = self.pdecode2
 681         dbg = self.dbg
 682         core = self.core
 683
 684         # set up peripherals and core
 685         core_rst = self.setup_peripherals(m)
 686
 687         # PC and instruction from I-Memory
 688         comb += self.pc_o.eq(cur_state.pc)
 689         pc_changed = Signal() # note write to PC
 690         sv_changed = Signal() # note write to SVSTATE
 691
 692         # read state either from incoming override or from regfile
 693         # TODO: really should be doing MSR in the same way
 694         pc = state_get(m, self.pc_i, "pc",                  # read PC
 695                             self.state_r_pc, StateRegs.PC)
 696         svstate = state_get(m, self.svstate_i, "svstate",   # read SVSTATE
 697                             self.state_r_sv, StateRegs.SVSTATE)
 698
 699         # don't write pc every cycle
 700         comb += self.state_w_pc.wen.eq(0)
 701         comb += self.state_w_pc.data_i.eq(0)
 702
 703         # don't read msr every cycle
 704         comb += self.state_r_msr.ren.eq(0)
 705
 706         # address of the next instruction, in the absence of a branch
 707         # depends on the instruction size
 708         nia = Signal(64, reset_less=True)
 709
 710         # connect up debug signals
 711         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 712         comb += dbg.terminate_i.eq(core.core_terminate_o)
 713         comb += dbg.state.pc.eq(pc)
 714         comb += dbg.state.svstate.eq(svstate)
 715         comb += dbg.state.msr.eq(cur_state.msr)
 716
 717         # pass the prefix mode from Fetch to Issue, so the latter can loop
 718         # on VL==0
 719         is_svp64_mode = Signal()
 720
 721         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 722         # these are the handshake signals between fetch and decode/execute
 723
 724         # fetch FSM can run as soon as the PC is valid
 725         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 726         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 727
 728         # fetch FSM hands over the instruction to be decoded / issued
 729         fetch_insn_valid_o = Signal()
 730         fetch_insn_ready_i = Signal()
 731
 732         # issue FSM delivers the instruction to the be executed
 733         exec_insn_valid_i = Signal()
 734         exec_insn_ready_o = Signal()
 735
 736         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 737         exec_pc_valid_o = Signal()
 738         exec_pc_ready_i = Signal()
 739
 740         # the FSMs here are perhaps unusual in that they detect conditions
 741         # then "hold" information, combinatorially, for the core
 742         # (as opposed to using sync - which would be on a clock's delay)
 743         # this includes the actual opcode, valid flags and so on.
 744
 745         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 746         # lives.  the ready/valid signalling is used to communicate between
 747         # the three.
 748
 749         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 750                        fetch_pc_ready_o, fetch_pc_valid_i,
 751                        fetch_insn_valid_o, fetch_insn_ready_i)
 752
 753         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 754                        dbg, core_rst, is_svp64_mode,
 755                        fetch_pc_ready_o, fetch_pc_valid_i,
 756                        fetch_insn_valid_o, fetch_insn_ready_i,
 757                        exec_insn_valid_i, exec_insn_ready_o,
 758                        exec_pc_valid_o, exec_pc_ready_i)
 759
 760         self.execute_fsm(m, core, pc_changed, sv_changed,
 761                          exec_insn_valid_i, exec_insn_ready_o,
 762                          exec_pc_valid_o, exec_pc_ready_i)
 763
 764         # this bit doesn't have to be in the FSM: connect up to read
 765         # regfiles on demand from DMI
 766         self.do_dmi(m, dbg)
 767
 768         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 769         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 770         self.tb_dec_fsm(m, cur_state.dec)
 771
 772         return m
 773
 774     def do_dmi(self, m, dbg):
 775         comb = m.d.comb
 776         sync = m.d.sync
 777         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 778         intrf = self.core.regs.rf['int']
 779
 780         with m.If(d_reg.req): # request for regfile access being made
 781             # TODO: error-check this
 782             # XXX should this be combinatorial?  sync better?
 783             if intrf.unary:
 784                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 785             else:
 786                 comb += self.int_r.addr.eq(d_reg.addr)
 787                 comb += self.int_r.ren.eq(1)
 788         d_reg_delay  = Signal()
 789         sync += d_reg_delay.eq(d_reg.req)
 790         with m.If(d_reg_delay):
 791             # data arrives one clock later
 792             comb += d_reg.data.eq(self.int_r.data_o)
 793             comb += d_reg.ack.eq(1)
 794
 795         # sigh same thing for CR debug
 796         with m.If(d_cr.req): # request for regfile access being made
 797             comb += self.cr_r.ren.eq(0b11111111) # enable all
 798         d_cr_delay  = Signal()
 799         sync += d_cr_delay.eq(d_cr.req)
 800         with m.If(d_cr_delay):
 801             # data arrives one clock later
 802             comb += d_cr.data.eq(self.cr_r.data_o)
 803             comb += d_cr.ack.eq(1)
 804
 805         # aaand XER...
 806         with m.If(d_xer.req): # request for regfile access being made
 807             comb += self.xer_r.ren.eq(0b111111) # enable all
 808         d_xer_delay  = Signal()
 809         sync += d_xer_delay.eq(d_xer.req)
 810         with m.If(d_xer_delay):
 811             # data arrives one clock later
 812             comb += d_xer.data.eq(self.xer_r.data_o)
 813             comb += d_xer.ack.eq(1)
 814
 815     def tb_dec_fsm(self, m, spr_dec):
 816         """tb_dec_fsm
 817
 818         this is a FSM for updating either dec or tb.  it runs alternately
 819         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 820         value to DEC, however the regfile has "passthrough" on it so this
 821         *should* be ok.
 822
 823         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 824         """
 825
 826         comb, sync = m.d.comb, m.d.sync
 827         fast_rf = self.core.regs.rf['fast']
 828         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 829         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 830
 831         with m.FSM() as fsm:
 832
 833             # initiates read of current DEC
 834             with m.State("DEC_READ"):
 835                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 836                 comb += fast_r_dectb.ren.eq(1)
 837                 m.next = "DEC_WRITE"
 838
 839             # waits for DEC read to arrive (1 cycle), updates with new value
 840             with m.State("DEC_WRITE"):
 841                 new_dec = Signal(64)
 842                 # TODO: MSR.LPCR 32-bit decrement mode
 843                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 844                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 845                 comb += fast_w_dectb.wen.eq(1)
 846                 comb += fast_w_dectb.data_i.eq(new_dec)
 847                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 848                 m.next = "TB_READ"
 849
 850             # initiates read of current TB
 851             with m.State("TB_READ"):
 852                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 853                 comb += fast_r_dectb.ren.eq(1)
 854                 m.next = "TB_WRITE"
 855
 856             # waits for read TB to arrive, initiates write of current TB
 857             with m.State("TB_WRITE"):
 858                 new_tb = Signal(64)
 859                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 860                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 861                 comb += fast_w_dectb.wen.eq(1)
 862                 comb += fast_w_dectb.data_i.eq(new_tb)
 863                 m.next = "DEC_READ"
 864
 865         return m
 866
 867     def __iter__(self):
 868         yield from self.pc_i.ports()
 869         yield self.pc_o
 870         yield self.memerr_o
 871         yield from self.core.ports()
 872         yield from self.imem.ports()
 873         yield self.core_bigendian_i
 874         yield self.busy_o
 875
 876     def ports(self):
 877         return list(self)
 878
 879     def external_ports(self):
 880         ports = self.pc_i.ports()
 881         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 882                 ]
 883
 884         if self.jtag_en:
 885             ports += list(self.jtag.external_ports())
 886         else:
 887             # don't add DMI if JTAG is enabled
 888             ports += list(self.dbg.dmi.ports())
 889
 890         ports += list(self.imem.ibus.fields.values())
 891         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 892
 893         if self.sram4x4k:
 894             for sram in self.sram4k:
 895                 ports += list(sram.bus.fields.values())
 896
 897         if self.xics:
 898             ports += list(self.xics_icp.bus.fields.values())
 899             ports += list(self.xics_ics.bus.fields.values())
 900             ports.append(self.int_level_i)
 901
 902         if self.gpio:
 903             ports += list(self.simple_gpio.bus.fields.values())
 904             ports.append(self.gpio_o)
 905
 906         return ports
 907
 908     def ports(self):
 909         return list(self)
 910
 911
 912 class TestIssuer(Elaboratable):
 913     def __init__(self, pspec):
 914         self.ti = TestIssuerInternal(pspec)
 915
 916         self.pll = DummyPLL()
 917
 918         # PLL direct clock or not
 919         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 920         if self.pll_en:
 921             self.pll_18_o = Signal(reset_less=True)
 922
 923     def elaborate(self, platform):
 924         m = Module()
 925         comb = m.d.comb
 926
 927         # TestIssuer runs at direct clock
 928         m.submodules.ti = ti = self.ti
 929         cd_int = ClockDomain("coresync")
 930
 931         if self.pll_en:
 932             # ClockSelect runs at PLL output internal clock rate
 933             m.submodules.pll = pll = self.pll
 934
 935             # add clock domains from PLL
 936             cd_pll = ClockDomain("pllclk")
 937             m.domains += cd_pll
 938
 939             # PLL clock established.  has the side-effect of running clklsel
 940             # at the PLL's speed (see DomainRenamer("pllclk") above)
 941             pllclk = ClockSignal("pllclk")
 942             comb += pllclk.eq(pll.clk_pll_o)
 943
 944             # wire up external 24mhz to PLL
 945             comb += pll.clk_24_i.eq(ClockSignal())
 946
 947             # output 18 mhz PLL test signal
 948             comb += self.pll_18_o.eq(pll.pll_18_o)
 949
 950             # now wire up ResetSignals.  don't mind them being in this domain
 951             pll_rst = ResetSignal("pllclk")
 952             comb += pll_rst.eq(ResetSignal())
 953
 954         # internal clock is set to selector clock-out.  has the side-effect of
 955         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 956         intclk = ClockSignal("coresync")
 957         if self.pll_en:
 958             comb += intclk.eq(pll.clk_pll_o)
 959         else:
 960             comb += intclk.eq(ClockSignal())
 961
 962         return m
 963
 964     def ports(self):
 965         return list(self.ti.ports()) + list(self.pll.ports()) + \
 966                [ClockSignal(), ResetSignal()]
 967
 968     def external_ports(self):
 969         ports = self.ti.external_ports()
 970         ports.append(ClockSignal())
 971         ports.append(ResetSignal())
 972         if self.pll_en:
 973             ports.append(self.pll.clk_sel_i)
 974             ports.append(self.pll_18_o)
 975             ports.append(self.pll.pll_lck_o)
 976         return ports
 977
 978
 979 if __name__ == '__main__':
 980     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 981              'spr': 1,
 982              'div': 1,
 983              'mul': 1,
 984              'shiftrot': 1
 985             }
 986     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 987                          imem_ifacetype='bare_wb',
 988                          addr_wid=48,
 989                          mask_wid=8,
 990                          reg_wid=64,
 991                          units=units)
 992     dut = TestIssuer(pspec)
 993     vl = main(dut, ports=dut.ports(), name="test_issuer")
 994
 995     if len(sys.argv) == 1:
 996         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 997         with open("test_issuer.il", "w") as f:
 998             f.write(vl)