src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2
  26 from soc.decoder.decode2execute1 import Data
  27 from soc.experiment.testmem import TestMemory # test only for instructions
  28 from soc.regfile.regfiles import StateRegs
  29 from soc.simple.core import NonProductionCore
  30 from soc.config.test.test_loadstore import TestMemPspec
  31 from soc.config.ifetch import ConfigFetchUnit
  32 from soc.decoder.power_enums import MicrOp
  33 from soc.debug.dmi import CoreDebug, DMIInterface
  34 from soc.config.state import CoreState
  35
  36 from nmutil.util import rising_edge
  37
  38
  39 class TestIssuer(Elaboratable):
  40     """TestIssuer - reads instructions from TestMemory and issues them
  41
  42     efficiency and speed is not the main goal here: functional correctness is.
  43     """
  44     def __init__(self, pspec):
  45         # main instruction core
  46         self.core = core = NonProductionCore(pspec)
  47
  48         # instruction decoder
  49         pdecode = create_pdecode()
  50         self.pdecode2 = PowerDecode2(pdecode)   # decoder
  51
  52         # Test Instruction memory
  53         self.imem = ConfigFetchUnit(pspec).fu
  54         # one-row cache of instruction read
  55         self.iline = Signal(64) # one instruction line
  56         self.iprev_adr = Signal(64) # previous address: if different, do read
  57
  58         # DMI interface
  59         self.dbg = CoreDebug()
  60
  61         # instruction go/monitor
  62         self.pc_o = Signal(64, reset_less=True)
  63         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  64         self.core_bigendian_i = Signal()
  65         self.busy_o = Signal(reset_less=True)
  66         self.memerr_o = Signal(reset_less=True)
  67
  68         # FAST regfile read /write ports for PC and MSR
  69         staterf = self.core.regs.rf['state']
  70         self.state_r_pc = staterf.r_ports['cia'] # PC rd
  71         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
  72         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
  73
  74         # DMI interface access
  75         intrf = self.core.regs.rf['int']
  76         crrf = self.core.regs.rf['cr']
  77         xerrf = self.core.regs.rf['xer']
  78         self.int_r = intrf.r_ports['dmi'] # INT read
  79         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
  80         self.xer_r = xerrf.r_ports['full_xer'] # XER read
  81
  82         # hack method of keeping an eye on whether branch/trap set the PC
  83         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
  84         self.state_nia.wen.name = 'state_nia_wen'
  85
  86     def elaborate(self, platform):
  87         m = Module()
  88         comb, sync = m.d.comb, m.d.sync
  89
  90         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  91         m.submodules.imem = imem = self.imem
  92         m.submodules.dbg = dbg = self.dbg
  93
  94         # instruction decoder
  95         pdecode = create_pdecode()
  96         m.submodules.dec2 = pdecode2 = self.pdecode2
  97
  98         # convenience
  99         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 100         intrf = self.core.regs.rf['int']
 101
 102         # clock delay power-on reset
 103         cd_por  = ClockDomain(reset_less=True)
 104         cd_sync = ClockDomain()
 105         core_sync = ClockDomain("coresync")
 106         m.domains += cd_por, cd_sync, core_sync
 107
 108         delay = Signal(range(4), reset=3)
 109         with m.If(delay != 0):
 110             m.d.por += delay.eq(delay - 1)
 111         comb += cd_por.clk.eq(ClockSignal())
 112         comb += core_sync.clk.eq(ClockSignal())
 113         # power-on reset delay
 114         comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
 115
 116         # busy/halted signals from core
 117         comb += self.busy_o.eq(core.busy_o)
 118         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 119
 120         # current state (MSR/PC at the moment
 121         cur_state = CoreState("cur")
 122
 123         # temporary hack: says "go" immediately for both address gen and ST
 124         l0 = core.l0
 125         ldst = core.fus.fus['ldst0']
 126         st_go_edge = rising_edge(m, ldst.st.rel_o)
 127         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 128         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 129
 130         # PC and instruction from I-Memory
 131         pc_changed = Signal() # note write to PC
 132         comb += self.pc_o.eq(cur_state.pc)
 133         ilatch = Signal(32)
 134
 135         # next instruction (+4 on current)
 136         nia = Signal(64, reset_less=True)
 137         comb += nia.eq(cur_state.pc + 4)
 138
 139         # read the PC
 140         pc = Signal(64, reset_less=True)
 141         pc_ok_delay = Signal()
 142         sync += pc_ok_delay.eq(~self.pc_i.ok)
 143         with m.If(self.pc_i.ok):
 144             # incoming override (start from pc_i)
 145             comb += pc.eq(self.pc_i.data)
 146         with m.Else():
 147             # otherwise read StateRegs regfile for PC...
 148             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 149         # ... but on a 1-clock delay
 150         with m.If(pc_ok_delay):
 151             comb += pc.eq(self.state_r_pc.data_o)
 152
 153         # don't write pc every cycle
 154         comb += self.state_w_pc.wen.eq(0)
 155         comb += self.state_w_pc.data_i.eq(0)
 156
 157         # don't read msr every cycle
 158         comb += self.state_r_msr.ren.eq(0)
 159
 160         # connect up debug signals
 161         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 162         comb += dbg.terminate_i.eq(core.core_terminate_o)
 163         comb += dbg.state.pc.eq(pc)
 164         #comb += dbg.state.pc.eq(cur_state.pc)
 165         comb += dbg.state.msr.eq(cur_state.msr)
 166
 167         # temporaries
 168         core_busy_o = core.busy_o                 # core is busy
 169         core_ivalid_i = core.ivalid_i             # instruction is valid
 170         core_issue_i = core.issue_i               # instruction is issued
 171         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 172
 173         insn_type = core.e.do.insn_type
 174         dec_state = pdecode2.state
 175
 176         # actually use a nmigen FSM for the first time (w00t)
 177         # this FSM is perhaps unusual in that it detects conditions
 178         # then "holds" information, combinatorially, for the core
 179         # (as opposed to using sync - which would be on a clock's delay)
 180         # this includes the actual opcode, valid flags and so on.
 181         with m.FSM() as fsm:
 182
 183             # waiting (zzz)
 184             with m.State("IDLE"):
 185                 sync += pc_changed.eq(0)
 186                 sync += core.e.eq(0)
 187                 with m.If(~dbg.core_stop_o & ~core.core_reset_i):
 188                     # instruction allowed to go: start by reading the PC
 189                     # capture the PC and also drop it into Insn Memory
 190                     # we have joined a pair of combinatorial memory
 191                     # lookups together.  this is Generally Bad.
 192                     comb += self.imem.a_pc_i.eq(pc)
 193                     comb += self.imem.a_valid_i.eq(1)
 194                     comb += self.imem.f_valid_i.eq(1)
 195                     sync += cur_state.pc.eq(pc)
 196
 197                     # initiate read of MSR
 198                     comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 199
 200                     m.next = "INSN_READ" # move to "wait for bus" phase
 201                 with m.Else():
 202                     comb += core.core_stopped_i.eq(1)
 203                     comb += dbg.core_stopped_i.eq(1)
 204
 205             # dummy pause to find out why simulation is not keeping up
 206             with m.State("INSN_READ"):
 207                 # one cycle later, msr read arrives
 208                 sync += cur_state.msr.eq(self.state_r_msr.data_o)
 209                 with m.If(self.imem.f_busy_o): # zzz...
 210                     # busy: stay in wait-read
 211                     comb += self.imem.a_valid_i.eq(1)
 212                     comb += self.imem.f_valid_i.eq(1)
 213                 with m.Else():
 214                     # not busy: instruction fetched
 215                     f_instr_o = self.imem.f_instr_o
 216                     if f_instr_o.width == 32:
 217                         insn = f_instr_o
 218                     else:
 219                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 220                     comb += dec_opcode_i.eq(insn) # actual opcode
 221                     comb += dec_state.eq(cur_state)
 222                     sync += core.e.eq(pdecode2.e)
 223                     sync += ilatch.eq(insn) # latch current insn
 224                     # also drop PC and MSR into decode "state"
 225                     m.next = "INSN_START" # move to "start"
 226
 227             # waiting for instruction bus (stays there until not busy)
 228             with m.State("INSN_START"):
 229                 comb += core_ivalid_i.eq(1) # instruction is valid
 230                 comb += core_issue_i.eq(1)  # and issued
 231
 232
 233                 m.next = "INSN_ACTIVE" # move to "wait completion"
 234
 235             # instruction started: must wait till it finishes
 236             with m.State("INSN_ACTIVE"):
 237                 with m.If(insn_type != MicrOp.OP_NOP):
 238                     comb += core_ivalid_i.eq(1) # instruction is valid
 239                 with m.If(self.state_nia.wen):
 240                     sync += pc_changed.eq(1)
 241                 with m.If(~core_busy_o): # instruction done!
 242                     # ok here we are not reading the branch unit.  TODO
 243                     # this just blithely overwrites whatever pipeline
 244                     # updated the PC
 245                     with m.If(~pc_changed):
 246                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 247                         comb += self.state_w_pc.data_i.eq(nia)
 248                     sync += core.e.eq(0)
 249                     m.next = "IDLE" # back to idle
 250
 251         # this bit doesn't have to be in the FSM: connect up to read
 252         # regfiles on demand from DMI
 253         with m.If(d_reg.req): # request for regfile access being made
 254             # TODO: error-check this
 255             # XXX should this be combinatorial?  sync better?
 256             if intrf.unary:
 257                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 258             else:
 259                 comb += self.int_r.addr.eq(d_reg.addr)
 260                 comb += self.int_r.ren.eq(1)
 261         d_reg_delay  = Signal()
 262         sync += d_reg_delay.eq(d_reg.req)
 263         with m.If(d_reg_delay):
 264             # data arrives one clock later
 265             comb += d_reg.data.eq(self.int_r.data_o)
 266             comb += d_reg.ack.eq(1)
 267
 268         # sigh same thing for CR debug
 269         with m.If(d_cr.req): # request for regfile access being made
 270             comb += self.cr_r.ren.eq(0b11111111) # enable all
 271         d_cr_delay  = Signal()
 272         sync += d_cr_delay.eq(d_cr.req)
 273         with m.If(d_cr_delay):
 274             # data arrives one clock later
 275             comb += d_cr.data.eq(self.cr_r.data_o)
 276             comb += d_cr.ack.eq(1)
 277
 278         # aaand XER...
 279         with m.If(d_xer.req): # request for regfile access being made
 280             comb += self.xer_r.ren.eq(0b111111) # enable all
 281         d_xer_delay  = Signal()
 282         sync += d_xer_delay.eq(d_xer.req)
 283         with m.If(d_xer_delay):
 284             # data arrives one clock later
 285             comb += d_xer.data.eq(self.xer_r.data_o)
 286             comb += d_xer.ack.eq(1)
 287
 288         return m
 289
 290     def __iter__(self):
 291         yield from self.pc_i.ports()
 292         yield self.pc_o
 293         yield self.memerr_o
 294         yield from self.core.ports()
 295         yield from self.imem.ports()
 296         yield self.core_bigendian_i
 297         yield self.busy_o
 298
 299     def ports(self):
 300         return list(self)
 301
 302     def external_ports(self):
 303         return self.pc_i.ports() + [self.pc_o,
 304                                     self.memerr_o,
 305                                     self.core_bigendian_i,
 306                                     ClockSignal(),
 307                                     ResetSignal(),
 308                                     self.busy_o,
 309                                     ] + \
 310                 list(self.dbg.dmi.ports()) + \
 311                 list(self.imem.ibus.fields.values()) + \
 312                 list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 313
 314     def ports(self):
 315         return list(self)
 316
 317
 318 if __name__ == '__main__':
 319     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 320              'spr': 1,
 321              'div': 1,
 322              'mul': 1,
 323              'shiftrot': 1
 324             }
 325     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 326                          imem_ifacetype='bare_wb',
 327                          addr_wid=48,
 328                          mask_wid=8,
 329                          reg_wid=64,
 330                          units=units)
 331     dut = TestIssuer(pspec)
 332     vl = main(dut, ports=dut.ports(), name="test_issuer")
 333
 334     if len(sys.argv) == 1:
 335         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 336         with open("test_issuer.il", "w") as f:
 337             f.write(vl)