src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55 # gets state input or reads from state regfile
  56 def state_get(m, state_i, name, regfile, regnum):
  57     comb = m.d.comb
  58     sync = m.d.sync
  59     # read the PC
  60     res = Signal(64, reset_less=True, name=name)
  61     res_ok_delay = Signal(name="%s_ok_delay" % name)
  62     sync += res_ok_delay.eq(~state_i.ok)
  63     with m.If(state_i.ok):
  64         # incoming override (start from pc_i)
  65         comb += res.eq(state_i.data)
  66     with m.Else():
  67         # otherwise read StateRegs regfile for PC...
  68         comb += regfile.ren.eq(1<<regnum)
  69     # ... but on a 1-clock delay
  70     with m.If(res_ok_delay):
  71         comb += res.eq(regfile.data_o)
  72     return res
  73
  74 def get_predint(m, mask):
  75     """decode SVP64 predicate integer mask field to reg number and invert
  76     this is identical to the equivalent function in ISACaller except that
  77     it doesn't read the INT directly, it just decodes "what needs to be done"
  78     i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
  79     """
  80     regread = Signal(5)
  81     invert = Signal()
  82     unary = Signal()
  83     with m.Switch(mask):
  84         with m.Case(SVP64PredInt.ALWAYS.value):
  85             comb += regread.eq(0)
  86             comb += invert.eq(1)
  87         with m.Case(SVP64PredInt.R3_UNARY.value):
  88             comb += regread.eq(3)
  89             comb += unary.eq(1)
  90         with m.Case(SVP64PredInt.R3.value):
  91             comb += regread.eq(3)
  92         with m.Case(SVP64PredInt.R3_N.value):
  93             comb += regread.eq(3)
  94             comb += invert.eq(1)
  95         with m.Case(SVP64PredInt.R10.value):
  96             comb += regread.eq(10)
  97         with m.Case(SVP64PredInt.R10_N.value):
  98             comb += regread.eq(10)
  99             comb += invert.eq(1)
 100         with m.Case(SVP64PredInt.R30.value):
 101             comb += regread.eq(30)
 102         with m.Case(SVP64PredInt.R30_N.value):
 103             comb += regread.eq(30)
 104             comb += invert.eq(1)
 105     return regread, invert, unary
 106
 107 def get_predcr(m, mask):
 108     """decode SVP64 predicate CR to reg number field and invert status
 109     this is identical to _get_predcr in ISACaller
 110     """
 111     idx = Signal(2)
 112     invert = Signal()
 113     with m.Switch(mask):
 114         with m.Case(SVP64PredCR.LT.value):
 115             comb += idx.eq(0)
 116             comb += invert.eq(1)
 117         with m.Case(SVP64PredCR.GE.value):
 118             comb += idx.eq(0)
 119             comb += invert.eq(0)
 120         with m.Case(SVP64PredCR.GT.value):
 121             comb += idx.eq(1)
 122             comb += invert.eq(1)
 123         with m.Case(SVP64PredCR.LE.value):
 124             comb += idx.eq(1)
 125             comb += invert.eq(0)
 126         with m.Case(SVP64PredCR.EQ.value):
 127             comb += idx.eq(2)
 128             comb += invert.eq(1)
 129         with m.Case(SVP64PredCR.NE.value):
 130             comb += idx.eq(1)
 131             comb += invert.eq(0)
 132         with m.Case(SVP64PredCR.SO.value):
 133             comb += idx.eq(3)
 134             comb += invert.eq(1)
 135         with m.Case(SVP64PredCR.NS.value):
 136             comb += idx.eq(3)
 137             comb += invert.eq(0)
 138     return idx, invert
 139
 140
 141 class TestIssuerInternal(Elaboratable):
 142     """TestIssuer - reads instructions from TestMemory and issues them
 143
 144     efficiency and speed is not the main goal here: functional correctness is.
 145     """
 146     def __init__(self, pspec):
 147
 148         # test is SVP64 is to be enabled
 149         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 150
 151         # JTAG interface.  add this right at the start because if it's
 152         # added it *modifies* the pspec, by adding enable/disable signals
 153         # for parts of the rest of the core
 154         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
 155         if self.jtag_en:
 156             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 157                       'pwm', 'sd0', 'sdr'}
 158             self.jtag = JTAG(get_pinspecs(subset=subset))
 159             # add signals to pspec to enable/disable icache and dcache
 160             # (or data and intstruction wishbone if icache/dcache not included)
 161             # https://bugs.libre-soc.org/show_bug.cgi?id=520
 162             # TODO: do we actually care if these are not domain-synchronised?
 163             # honestly probably not.
 164             pspec.wb_icache_en = self.jtag.wb_icache_en
 165             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 166             self.wb_sram_en = self.jtag.wb_sram_en
 167         else:
 168             self.wb_sram_en = Const(1)
 169
 170         # add 4k sram blocks?
 171         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
 172                          pspec.sram4x4kblock == True)
 173         if self.sram4x4k:
 174             self.sram4k = []
 175             for i in range(4):
 176                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
 177                                                     features={'err'}))
 178
 179         # add interrupt controller?
 180         self.xics = hasattr(pspec, "xics") and pspec.xics == True
 181         if self.xics:
 182             self.xics_icp = XICS_ICP()
 183             self.xics_ics = XICS_ICS()
 184             self.int_level_i = self.xics_ics.int_level_i
 185
 186         # add GPIO peripheral?
 187         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 188         if self.gpio:
 189             self.simple_gpio = SimpleGPIO()
 190             self.gpio_o = self.simple_gpio.gpio_o
 191
 192         # main instruction core.  suitable for prototyping / demo only
 193         self.core = core = NonProductionCore(pspec)
 194
 195         # instruction decoder.  goes into Trap Record
 196         pdecode = create_pdecode()
 197         self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
 198         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 199                                      opkls=IssuerDecode2ToOperand,
 200                                      svp64_en=self.svp64_en)
 201         if self.svp64_en:
 202             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 203
 204         # Test Instruction memory
 205         self.imem = ConfigFetchUnit(pspec).fu
 206
 207         # DMI interface
 208         self.dbg = CoreDebug()
 209
 210         # instruction go/monitor
 211         self.pc_o = Signal(64, reset_less=True)
 212         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 213         self.svstate_i = Data(32, "svstate_i") # ditto
 214         self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
 215         self.busy_o = Signal(reset_less=True)
 216         self.memerr_o = Signal(reset_less=True)
 217
 218         # STATE regfile read /write ports for PC, MSR, SVSTATE
 219         staterf = self.core.regs.rf['state']
 220         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 221         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 222         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 223         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 224         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 225
 226         # DMI interface access
 227         intrf = self.core.regs.rf['int']
 228         crrf = self.core.regs.rf['cr']
 229         xerrf = self.core.regs.rf['xer']
 230         self.int_r = intrf.r_ports['dmi'] # INT read
 231         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 232         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 233
 234         # for predication
 235         self.int_pred = intrf.r_ports['pred'] # INT predicate read
 236         self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
 237
 238         # hack method of keeping an eye on whether branch/trap set the PC
 239         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 240         self.state_nia.wen.name = 'state_nia_wen'
 241
 242         # pulse to synchronize the simulator at instruction end
 243         self.insn_done = Signal()
 244
 245         if self.svp64_en:
 246             # store copies of predicate masks
 247             self.srcmask = Signal(64)
 248             self.dstmask = Signal(64)
 249
 250     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 251                         fetch_pc_ready_o, fetch_pc_valid_i,
 252                         fetch_insn_valid_o, fetch_insn_ready_i):
 253         """fetch FSM
 254         this FSM performs fetch of raw instruction data, partial-decodes
 255         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 256         read a 2nd 32-bit quantity if that occurs.
 257         """
 258         comb = m.d.comb
 259         sync = m.d.sync
 260         pdecode2 = self.pdecode2
 261         cur_state = self.cur_state
 262         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 263
 264         msr_read = Signal(reset=1)
 265
 266         with m.FSM(name='fetch_fsm'):
 267
 268             # waiting (zzz)
 269             with m.State("IDLE"):
 270                 comb += fetch_pc_ready_o.eq(1)
 271                 with m.If(fetch_pc_valid_i):
 272                     # instruction allowed to go: start by reading the PC
 273                     # capture the PC and also drop it into Insn Memory
 274                     # we have joined a pair of combinatorial memory
 275                     # lookups together.  this is Generally Bad.
 276                     comb += self.imem.a_pc_i.eq(pc)
 277                     comb += self.imem.a_valid_i.eq(1)
 278                     comb += self.imem.f_valid_i.eq(1)
 279                     sync += cur_state.pc.eq(pc)
 280                     sync += cur_state.svstate.eq(svstate) # and svstate
 281
 282                     # initiate read of MSR. arrives one clock later
 283                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 284                     sync += msr_read.eq(0)
 285
 286                     m.next = "INSN_READ"  # move to "wait for bus" phase
 287
 288             # dummy pause to find out why simulation is not keeping up
 289             with m.State("INSN_READ"):
 290                 # one cycle later, msr/sv read arrives.  valid only once.
 291                 with m.If(~msr_read):
 292                     sync += msr_read.eq(1) # yeah don't read it again
 293                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 294                 with m.If(self.imem.f_busy_o): # zzz...
 295                     # busy: stay in wait-read
 296                     comb += self.imem.a_valid_i.eq(1)
 297                     comb += self.imem.f_valid_i.eq(1)
 298                 with m.Else():
 299                     # not busy: instruction fetched
 300                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 301                     if self.svp64_en:
 302                         svp64 = self.svp64
 303                         # decode the SVP64 prefix, if any
 304                         comb += svp64.raw_opcode_in.eq(insn)
 305                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 306                         # pass the decoded prefix (if any) to PowerDecoder2
 307                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 308                         # remember whether this is a prefixed instruction, so
 309                         # the FSM can readily loop when VL==0
 310                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 311                         # calculate the address of the following instruction
 312                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 313                         sync += nia.eq(cur_state.pc + insn_size)
 314                         with m.If(~svp64.is_svp64_mode):
 315                             # with no prefix, store the instruction
 316                             # and hand it directly to the next FSM
 317                             sync += dec_opcode_i.eq(insn)
 318                             m.next = "INSN_READY"
 319                         with m.Else():
 320                             # fetch the rest of the instruction from memory
 321                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 322                             comb += self.imem.a_valid_i.eq(1)
 323                             comb += self.imem.f_valid_i.eq(1)
 324                             m.next = "INSN_READ2"
 325                     else:
 326                         # not SVP64 - 32-bit only
 327                         sync += nia.eq(cur_state.pc + 4)
 328                         sync += dec_opcode_i.eq(insn)
 329                         m.next = "INSN_READY"
 330
 331             with m.State("INSN_READ2"):
 332                 with m.If(self.imem.f_busy_o):  # zzz...
 333                     # busy: stay in wait-read
 334                     comb += self.imem.a_valid_i.eq(1)
 335                     comb += self.imem.f_valid_i.eq(1)
 336                 with m.Else():
 337                     # not busy: instruction fetched
 338                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 339                     sync += dec_opcode_i.eq(insn)
 340                     m.next = "INSN_READY"
 341                     # TODO: probably can start looking at pdecode2.rm_dec
 342                     # here (or maybe even in INSN_READ state, if svp64_mode
 343                     # detected, in order to trigger - and wait for - the
 344                     # predicate reading.
 345
 346             with m.State("INSN_READY"):
 347                 # hand over the instruction, to be decoded
 348                 comb += fetch_insn_valid_o.eq(1)
 349                 with m.If(fetch_insn_ready_i):
 350                     m.next = "IDLE"
 351
 352     def fetch_predicate_fsm(self, m, core, TODO):
 353         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 354            src/dest predicate masks
 355
 356         https://bugs.libre-soc.org/show_bug.cgi?id=617
 357         the predicates can be read here, by using IntRegs r_ports['pred']
 358         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 359         be done through multiple reads, extracting one relevant at a time.
 360         later, a faster way would be to use the 32-bit-wide CR port but
 361         this is more complex decoding, here.  equivalent code used in
 362         ISACaller is "from soc.decoder.isa.caller import get_predcr"
 363         """
 364         comb = m.d.comb
 365         sync = m.d.sync
 366         pdecode2 = self.pdecode2
 367         rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
 368         predmode = rm_dec.predmode
 369         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 370         cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
 371         # if predmode == INT:
 372         #    INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
 373         #    INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
 374         #    TODO read INT-src and INT-dst into self.srcmask+dstmask
 375         # elif predmode == CR:
 376         #    CR-src sidx, sinvert = get_predcr(m, srcpred)
 377         #    CR-dst didx, dinvert = get_predcr(m, dstpred)
 378         #    TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
 379         # else
 380         #    sync += self.srcmask.eq(-1) # set to all 1s
 381         #    sync += self.dstmask.eq(-1) # set to all 1s
 382
 383     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 384                   dbg, core_rst, is_svp64_mode,
 385                   fetch_pc_ready_o, fetch_pc_valid_i,
 386                   fetch_insn_valid_o, fetch_insn_ready_i,
 387                   exec_insn_valid_i, exec_insn_ready_o,
 388                   exec_pc_valid_o, exec_pc_ready_i):
 389         """issue FSM
 390
 391         decode / issue FSM.  this interacts with the "fetch" FSM
 392         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 393         (outgoing). also interacts with the "execute" FSM
 394         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 395         (incoming).
 396         SVP64 RM prefixes have already been set up by the
 397         "fetch" phase, so execute is fairly straightforward.
 398         """
 399
 400         comb = m.d.comb
 401         sync = m.d.sync
 402         pdecode2 = self.pdecode2
 403         cur_state = self.cur_state
 404
 405         # temporaries
 406         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 407
 408         # for updating svstate (things like srcstep etc.)
 409         update_svstate = Signal() # set this (below) if updating
 410         new_svstate = SVSTATERec("new_svstate")
 411         comb += new_svstate.eq(cur_state.svstate)
 412
 413         with m.FSM(name="issue_fsm"):
 414
 415             # sync with the "fetch" phase which is reading the instruction
 416             # at this point, there is no instruction running, that
 417             # could inadvertently update the PC.
 418             with m.State("ISSUE_START"):
 419                 # wait on "core stop" release, before next fetch
 420                 # need to do this here, in case we are in a VL==0 loop
 421                 with m.If(~dbg.core_stop_o & ~core_rst):
 422                     comb += fetch_pc_valid_i.eq(1) # tell fetch to start
 423                     with m.If(fetch_pc_ready_o):   # fetch acknowledged us
 424                         m.next = "INSN_WAIT"
 425                 with m.Else():
 426                     # tell core it's stopped, and acknowledge debug handshake
 427                     comb += core.core_stopped_i.eq(1)
 428                     comb += dbg.core_stopped_i.eq(1)
 429                     # while stopped, allow updating the PC and SVSTATE
 430                     with m.If(self.pc_i.ok):
 431                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 432                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 433                         sync += pc_changed.eq(1)
 434                     with m.If(self.svstate_i.ok):
 435                         comb += new_svstate.eq(self.svstate_i.data)
 436                         comb += update_svstate.eq(1)
 437                         sync += sv_changed.eq(1)
 438
 439             # decode the instruction when it arrives
 440             with m.State("INSN_WAIT"):
 441                 comb += fetch_insn_ready_i.eq(1)
 442                 with m.If(fetch_insn_valid_o):
 443                     # decode the instruction
 444                     sync += core.e.eq(pdecode2.e)
 445                     sync += core.state.eq(cur_state)
 446                     sync += core.raw_insn_i.eq(dec_opcode_i)
 447                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 448                     # set RA_OR_ZERO detection in satellite decoders
 449                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 450                     # loop into ISSUE_START if it's a SVP64 instruction
 451                     # and VL == 0.  this because VL==0 is a for-loop
 452                     # from 0 to 0 i.e. always, always a NOP.
 453                     cur_vl = cur_state.svstate.vl
 454                     with m.If(is_svp64_mode & (cur_vl == 0)):
 455                         # update the PC before fetching the next instruction
 456                         # since we are in a VL==0 loop, no instruction was
 457                         # executed that we could be overwriting
 458                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 459                         comb += self.state_w_pc.data_i.eq(nia)
 460                         comb += self.insn_done.eq(1)
 461                         m.next = "ISSUE_START"
 462                     with m.Else():
 463                         m.next = "INSN_EXECUTE"  # move to "execute"
 464
 465             # handshake with execution FSM, move to "wait" once acknowledged
 466             with m.State("INSN_EXECUTE"):
 467                 # with m.If(is_svp64_mode):
 468                 #    TODO advance src/dst step to "skip" over predicated-out
 469                 #    from self.srcmask and self.dstmask
 470                 #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
 471                 #    but still without exceeding VL in either case
 472                 comb += exec_insn_valid_i.eq(1) # trigger execute
 473                 with m.If(exec_insn_ready_o):   # execute acknowledged us
 474                     m.next = "EXECUTE_WAIT"
 475
 476             with m.State("EXECUTE_WAIT"):
 477                 # wait on "core stop" release, at instruction end
 478                 # need to do this here, in case we are in a VL>1 loop
 479                 with m.If(~dbg.core_stop_o & ~core_rst):
 480                     comb += exec_pc_ready_i.eq(1)
 481                     with m.If(exec_pc_valid_o):
 482                         # precalculate srcstep+1 and dststep+1
 483                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 484                         next_dststep = Signal.like(cur_state.svstate.dststep)
 485                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 486                         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 487
 488                         # was this the last loop iteration?
 489                         is_last = Signal()
 490                         cur_vl = cur_state.svstate.vl
 491                         comb += is_last.eq(next_srcstep == cur_vl)
 492
 493                         # if either PC or SVSTATE were changed by the previous
 494                         # instruction, go directly back to Fetch, without
 495                         # updating either PC or SVSTATE
 496                         with m.If(pc_changed | sv_changed):
 497                             m.next = "ISSUE_START"
 498
 499                         # also return to Fetch, when no output was a vector
 500                         # (regardless of SRCSTEP and VL), or when the last
 501                         # instruction was really the last one of the VL loop
 502                         with m.Elif((~pdecode2.loop_continue) | is_last):
 503                             # before going back to fetch, update the PC state
 504                             # register with the NIA.
 505                             # ok here we are not reading the branch unit.
 506                             # TODO: this just blithely overwrites whatever
 507                             #       pipeline updated the PC
 508                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 509                             comb += self.state_w_pc.data_i.eq(nia)
 510                             # reset SRCSTEP before returning to Fetch
 511                             with m.If(pdecode2.loop_continue):
 512                                 comb += new_svstate.srcstep.eq(0)
 513                                 comb += new_svstate.dststep.eq(0)
 514                                 comb += update_svstate.eq(1)
 515                             m.next = "ISSUE_START"
 516
 517                         # returning to Execute? then, first update SRCSTEP
 518                         with m.Else():
 519                             comb += new_svstate.srcstep.eq(next_srcstep)
 520                             comb += new_svstate.dststep.eq(next_dststep)
 521                             comb += update_svstate.eq(1)
 522                             m.next = "DECODE_SV"
 523
 524                 with m.Else():
 525                     comb += core.core_stopped_i.eq(1)
 526                     comb += dbg.core_stopped_i.eq(1)
 527                     # while stopped, allow updating the PC and SVSTATE
 528                     with m.If(self.pc_i.ok):
 529                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 530                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 531                         sync += pc_changed.eq(1)
 532                     with m.If(self.svstate_i.ok):
 533                         comb += new_svstate.eq(self.svstate_i.data)
 534                         comb += update_svstate.eq(1)
 535                         sync += sv_changed.eq(1)
 536
 537             # need to decode the instruction again, after updating SRCSTEP
 538             # in the previous state.
 539             # mostly a copy of INSN_WAIT, but without the actual wait
 540             with m.State("DECODE_SV"):
 541                 # decode the instruction
 542                 sync += core.e.eq(pdecode2.e)
 543                 sync += core.state.eq(cur_state)
 544                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 545                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 546                 m.next = "INSN_EXECUTE"  # move to "execute"
 547
 548         # check if svstate needs updating: if so, write it to State Regfile
 549         with m.If(update_svstate):
 550             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 551             comb += self.state_w_sv.data_i.eq(new_svstate)
 552             sync += cur_state.svstate.eq(new_svstate) # for next clock
 553
 554     def execute_fsm(self, m, core, pc_changed, sv_changed,
 555                     exec_insn_valid_i, exec_insn_ready_o,
 556                     exec_pc_valid_o, exec_pc_ready_i):
 557         """execute FSM
 558
 559         execute FSM. this interacts with the "issue" FSM
 560         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 561         (outgoing). SVP64 RM prefixes have already been set up by the
 562         "issue" phase, so execute is fairly straightforward.
 563         """
 564
 565         comb = m.d.comb
 566         sync = m.d.sync
 567         pdecode2 = self.pdecode2
 568
 569         # temporaries
 570         core_busy_o = core.busy_o                 # core is busy
 571         core_ivalid_i = core.ivalid_i             # instruction is valid
 572         core_issue_i = core.issue_i               # instruction is issued
 573         insn_type = core.e.do.insn_type           # instruction MicroOp type
 574
 575         with m.FSM(name="exec_fsm"):
 576
 577             # waiting for instruction bus (stays there until not busy)
 578             with m.State("INSN_START"):
 579                 comb += exec_insn_ready_o.eq(1)
 580                 with m.If(exec_insn_valid_i):
 581                     comb += core_ivalid_i.eq(1)  # instruction is valid
 582                     comb += core_issue_i.eq(1)  # and issued
 583                     sync += sv_changed.eq(0)
 584                     sync += pc_changed.eq(0)
 585                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 586
 587             # instruction started: must wait till it finishes
 588             with m.State("INSN_ACTIVE"):
 589                 with m.If(insn_type != MicrOp.OP_NOP):
 590                     comb += core_ivalid_i.eq(1) # instruction is valid
 591                 # note changes to PC and SVSTATE
 592                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 593                     sync += sv_changed.eq(1)
 594                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 595                     sync += pc_changed.eq(1)
 596                 with m.If(~core_busy_o): # instruction done!
 597                     comb += exec_pc_valid_o.eq(1)
 598                     with m.If(exec_pc_ready_i):
 599                         comb += self.insn_done.eq(1)
 600                         m.next = "INSN_START"  # back to fetch
 601
 602     def setup_peripherals(self, m):
 603         comb, sync = m.d.comb, m.d.sync
 604
 605         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 606         m.submodules.imem = imem = self.imem
 607         m.submodules.dbg = dbg = self.dbg
 608         if self.jtag_en:
 609             m.submodules.jtag = jtag = self.jtag
 610             # TODO: UART2GDB mux, here, from external pin
 611             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 612             sync += dbg.dmi.connect_to(jtag.dmi)
 613
 614         cur_state = self.cur_state
 615
 616         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 617         if self.sram4x4k:
 618             for i, sram in enumerate(self.sram4k):
 619                 m.submodules["sram4k_%d" % i] = sram
 620                 comb += sram.enable.eq(self.wb_sram_en)
 621
 622         # XICS interrupt handler
 623         if self.xics:
 624             m.submodules.xics_icp = icp = self.xics_icp
 625             m.submodules.xics_ics = ics = self.xics_ics
 626             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 627             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 628
 629         # GPIO test peripheral
 630         if self.gpio:
 631             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 632
 633         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 634         # XXX causes litex ECP5 test to get wrong idea about input and output
 635         # (but works with verilator sim *sigh*)
 636         #if self.gpio and self.xics:
 637         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 638
 639         # instruction decoder
 640         pdecode = create_pdecode()
 641         m.submodules.dec2 = pdecode2 = self.pdecode2
 642         if self.svp64_en:
 643             m.submodules.svp64 = svp64 = self.svp64
 644
 645         # convenience
 646         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 647         intrf = self.core.regs.rf['int']
 648
 649         # clock delay power-on reset
 650         cd_por  = ClockDomain(reset_less=True)
 651         cd_sync = ClockDomain()
 652         core_sync = ClockDomain("coresync")
 653         m.domains += cd_por, cd_sync, core_sync
 654
 655         ti_rst = Signal(reset_less=True)
 656         delay = Signal(range(4), reset=3)
 657         with m.If(delay != 0):
 658             m.d.por += delay.eq(delay - 1)
 659         comb += cd_por.clk.eq(ClockSignal())
 660
 661         # power-on reset delay
 662         core_rst = ResetSignal("coresync")
 663         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 664         comb += core_rst.eq(ti_rst)
 665
 666         # busy/halted signals from core
 667         comb += self.busy_o.eq(core.busy_o)
 668         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 669
 670         # temporary hack: says "go" immediately for both address gen and ST
 671         l0 = core.l0
 672         ldst = core.fus.fus['ldst0']
 673         st_go_edge = rising_edge(m, ldst.st.rel_o)
 674         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 675         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 676
 677         return core_rst
 678
 679     def elaborate(self, platform):
 680         m = Module()
 681         # convenience
 682         comb, sync = m.d.comb, m.d.sync
 683         cur_state = self.cur_state
 684         pdecode2 = self.pdecode2
 685         dbg = self.dbg
 686         core = self.core
 687
 688         # set up peripherals and core
 689         core_rst = self.setup_peripherals(m)
 690
 691         # PC and instruction from I-Memory
 692         comb += self.pc_o.eq(cur_state.pc)
 693         pc_changed = Signal() # note write to PC
 694         sv_changed = Signal() # note write to SVSTATE
 695
 696         # read state either from incoming override or from regfile
 697         # TODO: really should be doing MSR in the same way
 698         pc = state_get(m, self.pc_i, "pc",                  # read PC
 699                             self.state_r_pc, StateRegs.PC)
 700         svstate = state_get(m, self.svstate_i, "svstate",   # read SVSTATE
 701                             self.state_r_sv, StateRegs.SVSTATE)
 702
 703         # don't write pc every cycle
 704         comb += self.state_w_pc.wen.eq(0)
 705         comb += self.state_w_pc.data_i.eq(0)
 706
 707         # don't read msr every cycle
 708         comb += self.state_r_msr.ren.eq(0)
 709
 710         # address of the next instruction, in the absence of a branch
 711         # depends on the instruction size
 712         nia = Signal(64, reset_less=True)
 713
 714         # connect up debug signals
 715         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 716         comb += dbg.terminate_i.eq(core.core_terminate_o)
 717         comb += dbg.state.pc.eq(pc)
 718         comb += dbg.state.svstate.eq(svstate)
 719         comb += dbg.state.msr.eq(cur_state.msr)
 720
 721         # pass the prefix mode from Fetch to Issue, so the latter can loop
 722         # on VL==0
 723         is_svp64_mode = Signal()
 724
 725         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 726         # these are the handshake signals between fetch and decode/execute
 727
 728         # fetch FSM can run as soon as the PC is valid
 729         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 730         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 731
 732         # fetch FSM hands over the instruction to be decoded / issued
 733         fetch_insn_valid_o = Signal()
 734         fetch_insn_ready_i = Signal()
 735
 736         # issue FSM delivers the instruction to the be executed
 737         exec_insn_valid_i = Signal()
 738         exec_insn_ready_o = Signal()
 739
 740         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 741         exec_pc_valid_o = Signal()
 742         exec_pc_ready_i = Signal()
 743
 744         # the FSMs here are perhaps unusual in that they detect conditions
 745         # then "hold" information, combinatorially, for the core
 746         # (as opposed to using sync - which would be on a clock's delay)
 747         # this includes the actual opcode, valid flags and so on.
 748
 749         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 750         # lives.  the ready/valid signalling is used to communicate between
 751         # the three.
 752
 753         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 754                        fetch_pc_ready_o, fetch_pc_valid_i,
 755                        fetch_insn_valid_o, fetch_insn_ready_i)
 756
 757         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 758                        dbg, core_rst, is_svp64_mode,
 759                        fetch_pc_ready_o, fetch_pc_valid_i,
 760                        fetch_insn_valid_o, fetch_insn_ready_i,
 761                        exec_insn_valid_i, exec_insn_ready_o,
 762                        exec_pc_valid_o, exec_pc_ready_i)
 763
 764         self.execute_fsm(m, core, pc_changed, sv_changed,
 765                          exec_insn_valid_i, exec_insn_ready_o,
 766                          exec_pc_valid_o, exec_pc_ready_i)
 767
 768         # this bit doesn't have to be in the FSM: connect up to read
 769         # regfiles on demand from DMI
 770         self.do_dmi(m, dbg)
 771
 772         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 773         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 774         self.tb_dec_fsm(m, cur_state.dec)
 775
 776         return m
 777
 778     def do_dmi(self, m, dbg):
 779         comb = m.d.comb
 780         sync = m.d.sync
 781         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 782         intrf = self.core.regs.rf['int']
 783
 784         with m.If(d_reg.req): # request for regfile access being made
 785             # TODO: error-check this
 786             # XXX should this be combinatorial?  sync better?
 787             if intrf.unary:
 788                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 789             else:
 790                 comb += self.int_r.addr.eq(d_reg.addr)
 791                 comb += self.int_r.ren.eq(1)
 792         d_reg_delay  = Signal()
 793         sync += d_reg_delay.eq(d_reg.req)
 794         with m.If(d_reg_delay):
 795             # data arrives one clock later
 796             comb += d_reg.data.eq(self.int_r.data_o)
 797             comb += d_reg.ack.eq(1)
 798
 799         # sigh same thing for CR debug
 800         with m.If(d_cr.req): # request for regfile access being made
 801             comb += self.cr_r.ren.eq(0b11111111) # enable all
 802         d_cr_delay  = Signal()
 803         sync += d_cr_delay.eq(d_cr.req)
 804         with m.If(d_cr_delay):
 805             # data arrives one clock later
 806             comb += d_cr.data.eq(self.cr_r.data_o)
 807             comb += d_cr.ack.eq(1)
 808
 809         # aaand XER...
 810         with m.If(d_xer.req): # request for regfile access being made
 811             comb += self.xer_r.ren.eq(0b111111) # enable all
 812         d_xer_delay  = Signal()
 813         sync += d_xer_delay.eq(d_xer.req)
 814         with m.If(d_xer_delay):
 815             # data arrives one clock later
 816             comb += d_xer.data.eq(self.xer_r.data_o)
 817             comb += d_xer.ack.eq(1)
 818
 819     def tb_dec_fsm(self, m, spr_dec):
 820         """tb_dec_fsm
 821
 822         this is a FSM for updating either dec or tb.  it runs alternately
 823         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 824         value to DEC, however the regfile has "passthrough" on it so this
 825         *should* be ok.
 826
 827         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 828         """
 829
 830         comb, sync = m.d.comb, m.d.sync
 831         fast_rf = self.core.regs.rf['fast']
 832         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 833         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 834
 835         with m.FSM() as fsm:
 836
 837             # initiates read of current DEC
 838             with m.State("DEC_READ"):
 839                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 840                 comb += fast_r_dectb.ren.eq(1)
 841                 m.next = "DEC_WRITE"
 842
 843             # waits for DEC read to arrive (1 cycle), updates with new value
 844             with m.State("DEC_WRITE"):
 845                 new_dec = Signal(64)
 846                 # TODO: MSR.LPCR 32-bit decrement mode
 847                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 848                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 849                 comb += fast_w_dectb.wen.eq(1)
 850                 comb += fast_w_dectb.data_i.eq(new_dec)
 851                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 852                 m.next = "TB_READ"
 853
 854             # initiates read of current TB
 855             with m.State("TB_READ"):
 856                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 857                 comb += fast_r_dectb.ren.eq(1)
 858                 m.next = "TB_WRITE"
 859
 860             # waits for read TB to arrive, initiates write of current TB
 861             with m.State("TB_WRITE"):
 862                 new_tb = Signal(64)
 863                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 864                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 865                 comb += fast_w_dectb.wen.eq(1)
 866                 comb += fast_w_dectb.data_i.eq(new_tb)
 867                 m.next = "DEC_READ"
 868
 869         return m
 870
 871     def __iter__(self):
 872         yield from self.pc_i.ports()
 873         yield self.pc_o
 874         yield self.memerr_o
 875         yield from self.core.ports()
 876         yield from self.imem.ports()
 877         yield self.core_bigendian_i
 878         yield self.busy_o
 879
 880     def ports(self):
 881         return list(self)
 882
 883     def external_ports(self):
 884         ports = self.pc_i.ports()
 885         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 886                 ]
 887
 888         if self.jtag_en:
 889             ports += list(self.jtag.external_ports())
 890         else:
 891             # don't add DMI if JTAG is enabled
 892             ports += list(self.dbg.dmi.ports())
 893
 894         ports += list(self.imem.ibus.fields.values())
 895         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 896
 897         if self.sram4x4k:
 898             for sram in self.sram4k:
 899                 ports += list(sram.bus.fields.values())
 900
 901         if self.xics:
 902             ports += list(self.xics_icp.bus.fields.values())
 903             ports += list(self.xics_ics.bus.fields.values())
 904             ports.append(self.int_level_i)
 905
 906         if self.gpio:
 907             ports += list(self.simple_gpio.bus.fields.values())
 908             ports.append(self.gpio_o)
 909
 910         return ports
 911
 912     def ports(self):
 913         return list(self)
 914
 915
 916 class TestIssuer(Elaboratable):
 917     def __init__(self, pspec):
 918         self.ti = TestIssuerInternal(pspec)
 919
 920         self.pll = DummyPLL()
 921
 922         # PLL direct clock or not
 923         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 924         if self.pll_en:
 925             self.pll_18_o = Signal(reset_less=True)
 926
 927     def elaborate(self, platform):
 928         m = Module()
 929         comb = m.d.comb
 930
 931         # TestIssuer runs at direct clock
 932         m.submodules.ti = ti = self.ti
 933         cd_int = ClockDomain("coresync")
 934
 935         if self.pll_en:
 936             # ClockSelect runs at PLL output internal clock rate
 937             m.submodules.pll = pll = self.pll
 938
 939             # add clock domains from PLL
 940             cd_pll = ClockDomain("pllclk")
 941             m.domains += cd_pll
 942
 943             # PLL clock established.  has the side-effect of running clklsel
 944             # at the PLL's speed (see DomainRenamer("pllclk") above)
 945             pllclk = ClockSignal("pllclk")
 946             comb += pllclk.eq(pll.clk_pll_o)
 947
 948             # wire up external 24mhz to PLL
 949             comb += pll.clk_24_i.eq(ClockSignal())
 950
 951             # output 18 mhz PLL test signal
 952             comb += self.pll_18_o.eq(pll.pll_18_o)
 953
 954             # now wire up ResetSignals.  don't mind them being in this domain
 955             pll_rst = ResetSignal("pllclk")
 956             comb += pll_rst.eq(ResetSignal())
 957
 958         # internal clock is set to selector clock-out.  has the side-effect of
 959         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 960         intclk = ClockSignal("coresync")
 961         if self.pll_en:
 962             comb += intclk.eq(pll.clk_pll_o)
 963         else:
 964             comb += intclk.eq(ClockSignal())
 965
 966         return m
 967
 968     def ports(self):
 969         return list(self.ti.ports()) + list(self.pll.ports()) + \
 970                [ClockSignal(), ResetSignal()]
 971
 972     def external_ports(self):
 973         ports = self.ti.external_ports()
 974         ports.append(ClockSignal())
 975         ports.append(ResetSignal())
 976         if self.pll_en:
 977             ports.append(self.pll.clk_sel_i)
 978             ports.append(self.pll_18_o)
 979             ports.append(self.pll.pll_lck_o)
 980         return ports
 981
 982
 983 if __name__ == '__main__':
 984     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 985              'spr': 1,
 986              'div': 1,
 987              'mul': 1,
 988              'shiftrot': 1
 989             }
 990     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 991                          imem_ifacetype='bare_wb',
 992                          addr_wid=48,
 993                          mask_wid=8,
 994                          reg_wid=64,
 995                          units=units)
 996     dut = TestIssuer(pspec)
 997     vl = main(dut, ports=dut.ports(), name="test_issuer")
 998
 999     if len(sys.argv) == 1:
1000         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1001         with open("test_issuer.il", "w") as f:
1002             f.write(vl)