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[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from soc.decoder.power_decoder import create_pdecode
25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
27 from soc.decoder.decode2execute1 import Data
28 from soc.experiment.testmem import TestMemory # test only for instructions
29 from soc.regfile.regfiles import StateRegs, FastRegs
30 from soc.simple.core import NonProductionCore
31 from soc.config.test.test_loadstore import TestMemPspec
32 from soc.config.ifetch import ConfigFetchUnit
33 from soc.decoder.power_enums import MicrOp
34 from soc.debug.dmi import CoreDebug, DMIInterface
35 from soc.debug.jtag import JTAG
36 from soc.config.pinouts import get_pinspecs
37 from soc.config.state import CoreState
38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
39 from soc.bus.simple_gpio import SimpleGPIO
40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
41 from soc.clock.select import ClockSelect
42 from soc.clock.dummypll import DummyPLL
43 from soc.sv.svstate import SVSTATERec
44
45
46 from nmutil.util import rising_edge
47
48 def get_insn(f_instr_o, pc):
49 if f_instr_o.width == 32:
50 return f_instr_o
51 else:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o.word_select(pc[2], 32)
54
55 # gets state input or reads from state regfile
56 def state_get(m, state_i, name, regfile, regnum):
57 comb = m.d.comb
58 sync = m.d.sync
59 # read the PC
60 res = Signal(64, reset_less=True, name=name)
61 res_ok_delay = Signal(name="%s_ok_delay" % name)
62 sync += res_ok_delay.eq(~state_i.ok)
63 with m.If(state_i.ok):
64 # incoming override (start from pc_i)
65 comb += res.eq(state_i.data)
66 with m.Else():
67 # otherwise read StateRegs regfile for PC...
68 comb += regfile.ren.eq(1<<regnum)
69 # ... but on a 1-clock delay
70 with m.If(res_ok_delay):
71 comb += res.eq(regfile.data_o)
72 return res
73
74 def get_predint(m, mask):
75 """decode SVP64 predicate integer mask field to reg number and invert
76 this is identical to the equivalent function in ISACaller except that
77 it doesn't read the INT directly, it just decodes "what needs to be done"
78 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
79 """
80 regread = Signal(5)
81 invert = Signal()
82 unary = Signal()
83 with m.Switch(mask):
84 with m.Case(SVP64PredInt.ALWAYS.value):
85 comb += regread.eq(0)
86 comb += invert.eq(1)
87 with m.Case(SVP64PredInt.R3_UNARY.value):
88 comb += regread.eq(3)
89 comb += unary.eq(1)
90 with m.Case(SVP64PredInt.R3.value):
91 comb += regread.eq(3)
92 with m.Case(SVP64PredInt.R3_N.value):
93 comb += regread.eq(3)
94 comb += invert.eq(1)
95 with m.Case(SVP64PredInt.R10.value):
96 comb += regread.eq(10)
97 with m.Case(SVP64PredInt.R10_N.value):
98 comb += regread.eq(10)
99 comb += invert.eq(1)
100 with m.Case(SVP64PredInt.R30.value):
101 comb += regread.eq(30)
102 with m.Case(SVP64PredInt.R30_N.value):
103 comb += regread.eq(30)
104 comb += invert.eq(1)
105 return regread, invert, unary
106
107 def get_predcr(m, mask):
108 """decode SVP64 predicate CR to reg number field and invert status
109 this is identical to _get_predcr in ISACaller
110 """
111 idx = Signal(2)
112 invert = Signal()
113 with m.Switch(mask):
114 with m.Case(SVP64PredCR.LT.value):
115 comb += idx.eq(0)
116 comb += invert.eq(1)
117 with m.Case(SVP64PredCR.GE.value):
118 comb += idx.eq(0)
119 comb += invert.eq(0)
120 with m.Case(SVP64PredCR.GT.value):
121 comb += idx.eq(1)
122 comb += invert.eq(1)
123 with m.Case(SVP64PredCR.LE.value):
124 comb += idx.eq(1)
125 comb += invert.eq(0)
126 with m.Case(SVP64PredCR.EQ.value):
127 comb += idx.eq(2)
128 comb += invert.eq(1)
129 with m.Case(SVP64PredCR.NE.value):
130 comb += idx.eq(1)
131 comb += invert.eq(0)
132 with m.Case(SVP64PredCR.SO.value):
133 comb += idx.eq(3)
134 comb += invert.eq(1)
135 with m.Case(SVP64PredCR.NS.value):
136 comb += idx.eq(3)
137 comb += invert.eq(0)
138 return idx, invert
139
140
141 class TestIssuerInternal(Elaboratable):
142 """TestIssuer - reads instructions from TestMemory and issues them
143
144 efficiency and speed is not the main goal here: functional correctness
145 and code clarity is. optimisations (which almost 100% interfere with
146 easy understanding) come later.
147 """
148 def __init__(self, pspec):
149
150 # test is SVP64 is to be enabled
151 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
152
153 # JTAG interface. add this right at the start because if it's
154 # added it *modifies* the pspec, by adding enable/disable signals
155 # for parts of the rest of the core
156 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
157 if self.jtag_en:
158 subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
159 'pwm', 'sd0', 'sdr'}
160 self.jtag = JTAG(get_pinspecs(subset=subset))
161 # add signals to pspec to enable/disable icache and dcache
162 # (or data and intstruction wishbone if icache/dcache not included)
163 # https://bugs.libre-soc.org/show_bug.cgi?id=520
164 # TODO: do we actually care if these are not domain-synchronised?
165 # honestly probably not.
166 pspec.wb_icache_en = self.jtag.wb_icache_en
167 pspec.wb_dcache_en = self.jtag.wb_dcache_en
168 self.wb_sram_en = self.jtag.wb_sram_en
169 else:
170 self.wb_sram_en = Const(1)
171
172 # add 4k sram blocks?
173 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
174 pspec.sram4x4kblock == True)
175 if self.sram4x4k:
176 self.sram4k = []
177 for i in range(4):
178 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
179 features={'err'}))
180
181 # add interrupt controller?
182 self.xics = hasattr(pspec, "xics") and pspec.xics == True
183 if self.xics:
184 self.xics_icp = XICS_ICP()
185 self.xics_ics = XICS_ICS()
186 self.int_level_i = self.xics_ics.int_level_i
187
188 # add GPIO peripheral?
189 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
190 if self.gpio:
191 self.simple_gpio = SimpleGPIO()
192 self.gpio_o = self.simple_gpio.gpio_o
193
194 # main instruction core. suitable for prototyping / demo only
195 self.core = core = NonProductionCore(pspec)
196
197 # instruction decoder. goes into Trap Record
198 pdecode = create_pdecode()
199 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
200 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
201 opkls=IssuerDecode2ToOperand,
202 svp64_en=self.svp64_en)
203 if self.svp64_en:
204 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
205
206 # Test Instruction memory
207 self.imem = ConfigFetchUnit(pspec).fu
208
209 # DMI interface
210 self.dbg = CoreDebug()
211
212 # instruction go/monitor
213 self.pc_o = Signal(64, reset_less=True)
214 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
215 self.svstate_i = Data(32, "svstate_i") # ditto
216 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
217 self.busy_o = Signal(reset_less=True)
218 self.memerr_o = Signal(reset_less=True)
219
220 # STATE regfile read /write ports for PC, MSR, SVSTATE
221 staterf = self.core.regs.rf['state']
222 self.state_r_pc = staterf.r_ports['cia'] # PC rd
223 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
224 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
225 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
226 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
227
228 # DMI interface access
229 intrf = self.core.regs.rf['int']
230 crrf = self.core.regs.rf['cr']
231 xerrf = self.core.regs.rf['xer']
232 self.int_r = intrf.r_ports['dmi'] # INT read
233 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
234 self.xer_r = xerrf.r_ports['full_xer'] # XER read
235
236 # for predication
237 self.int_pred = intrf.r_ports['pred'] # INT predicate read
238 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
239
240 # hack method of keeping an eye on whether branch/trap set the PC
241 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
242 self.state_nia.wen.name = 'state_nia_wen'
243
244 # pulse to synchronize the simulator at instruction end
245 self.insn_done = Signal()
246
247 if self.svp64_en:
248 # store copies of predicate masks
249 self.srcmask = Signal(64)
250 self.dstmask = Signal(64)
251
252 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
253 fetch_pc_ready_o, fetch_pc_valid_i,
254 fetch_insn_valid_o, fetch_insn_ready_i):
255 """fetch FSM
256
257 this FSM performs fetch of raw instruction data, partial-decodes
258 it 32-bit at a time to detect SVP64 prefixes, and will optionally
259 read a 2nd 32-bit quantity if that occurs.
260 """
261 comb = m.d.comb
262 sync = m.d.sync
263 pdecode2 = self.pdecode2
264 cur_state = self.cur_state
265 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
266
267 msr_read = Signal(reset=1)
268
269 with m.FSM(name='fetch_fsm'):
270
271 # waiting (zzz)
272 with m.State("IDLE"):
273 comb += fetch_pc_ready_o.eq(1)
274 with m.If(fetch_pc_valid_i):
275 # instruction allowed to go: start by reading the PC
276 # capture the PC and also drop it into Insn Memory
277 # we have joined a pair of combinatorial memory
278 # lookups together. this is Generally Bad.
279 comb += self.imem.a_pc_i.eq(pc)
280 comb += self.imem.a_valid_i.eq(1)
281 comb += self.imem.f_valid_i.eq(1)
282 sync += cur_state.pc.eq(pc)
283 sync += cur_state.svstate.eq(svstate) # and svstate
284
285 # initiate read of MSR. arrives one clock later
286 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
287 sync += msr_read.eq(0)
288
289 m.next = "INSN_READ" # move to "wait for bus" phase
290
291 # dummy pause to find out why simulation is not keeping up
292 with m.State("INSN_READ"):
293 # one cycle later, msr/sv read arrives. valid only once.
294 with m.If(~msr_read):
295 sync += msr_read.eq(1) # yeah don't read it again
296 sync += cur_state.msr.eq(self.state_r_msr.data_o)
297 with m.If(self.imem.f_busy_o): # zzz...
298 # busy: stay in wait-read
299 comb += self.imem.a_valid_i.eq(1)
300 comb += self.imem.f_valid_i.eq(1)
301 with m.Else():
302 # not busy: instruction fetched
303 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
304 if self.svp64_en:
305 svp64 = self.svp64
306 # decode the SVP64 prefix, if any
307 comb += svp64.raw_opcode_in.eq(insn)
308 comb += svp64.bigendian.eq(self.core_bigendian_i)
309 # pass the decoded prefix (if any) to PowerDecoder2
310 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
311 # remember whether this is a prefixed instruction, so
312 # the FSM can readily loop when VL==0
313 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
314 # calculate the address of the following instruction
315 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
316 sync += nia.eq(cur_state.pc + insn_size)
317 with m.If(~svp64.is_svp64_mode):
318 # with no prefix, store the instruction
319 # and hand it directly to the next FSM
320 sync += dec_opcode_i.eq(insn)
321 m.next = "INSN_READY"
322 with m.Else():
323 # fetch the rest of the instruction from memory
324 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
325 comb += self.imem.a_valid_i.eq(1)
326 comb += self.imem.f_valid_i.eq(1)
327 m.next = "INSN_READ2"
328 else:
329 # not SVP64 - 32-bit only
330 sync += nia.eq(cur_state.pc + 4)
331 sync += dec_opcode_i.eq(insn)
332 m.next = "INSN_READY"
333
334 with m.State("INSN_READ2"):
335 with m.If(self.imem.f_busy_o): # zzz...
336 # busy: stay in wait-read
337 comb += self.imem.a_valid_i.eq(1)
338 comb += self.imem.f_valid_i.eq(1)
339 with m.Else():
340 # not busy: instruction fetched
341 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
342 sync += dec_opcode_i.eq(insn)
343 m.next = "INSN_READY"
344 # TODO: probably can start looking at pdecode2.rm_dec
345 # here or maybe even in INSN_READ state, if svp64_mode
346 # detected, in order to trigger - and wait for - the
347 # predicate reading.
348 pmode = pdecode2.rm_dec.predmode
349 """
350 if pmode != SVP64PredMode.ALWAYS.value:
351 fire predicate loading FSM and wait before
352 moving to INSN_READY
353 else:
354 sync += self.srcmask.eq(-1) # set to all 1s
355 sync += self.dstmask.eq(-1) # set to all 1s
356 m.next = "INSN_READY"
357 """
358
359 with m.State("INSN_READY"):
360 # hand over the instruction, to be decoded
361 comb += fetch_insn_valid_o.eq(1)
362 with m.If(fetch_insn_ready_i):
363 m.next = "IDLE"
364
365 def fetch_predicate_fsm(self, m,
366 pred_insn_valid_i, pred_insn_ready_o,
367 pred_mask_valid_o, pred_mask_ready_i):
368 """fetch_predicate_fsm - obtains (constructs in the case of CR)
369 src/dest predicate masks
370
371 https://bugs.libre-soc.org/show_bug.cgi?id=617
372 the predicates can be read here, by using IntRegs r_ports['pred']
373 or CRRegs r_ports['pred']. in the case of CRs it will have to
374 be done through multiple reads, extracting one relevant at a time.
375 later, a faster way would be to use the 32-bit-wide CR port but
376 this is more complex decoding, here. equivalent code used in
377 ISACaller is "from soc.decoder.isa.caller import get_predcr"
378 """
379 comb = m.d.comb
380 sync = m.d.sync
381 pdecode2 = self.pdecode2
382 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
383 predmode = rm_dec.predmode
384 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
385 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
386 # if predmode == INT:
387 # INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
388 # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
389 # TODO read INT-src and INT-dst into self.srcmask+dstmask
390 # has to cope with first one then the other
391 # FSM-triggered-int-read
392 # comb += int_pred.addr.eq(d_reg.addr)
393 # comb += int_pred.ren.eq(1)
394 # FSM-1-clock-later
395 # comb += d_reg.data.eq(self.int_r.data_o)
396 # elif predmode == CR:
397 # CR-src sidx, sinvert = get_predcr(m, srcpred)
398 # CR-dst didx, dinvert = get_predcr(m, dstpred)
399 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
400 # has to cope with first one then the other
401 # for cr_idx = FSM-state-loop(0..VL-1):
402 # FSM-state-trigger-CR-read:
403 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
404 # comb += cr_pred.ren.eq(cr_ren)
405 # FSM-state-1-clock-later-actual-Read:
406 # cr_field = Signal(4)
407 # cr_bit = Signal(1)
408 # # read the CR field, select the appropriate bit
409 # comb += cr_field.eq(cr_pred.data_o)
410 # comb += cr_bit.eq(cr_field.bit_select(idx)))
411 # # just like in branch BO tests
412 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
413 # else
414 # sync += self.srcmask.eq(-1) # set to all 1s
415 # sync += self.dstmask.eq(-1) # set to all 1s
416 with m.FSM(name="fetch_predicate"):
417
418 with m.State("FETCH_PRED_IDLE"):
419 comb += pred_insn_ready_o.eq(1)
420 with m.If(pred_insn_valid_i):
421 sync += self.srcmask.eq(-1)
422 sync += self.dstmask.eq(-1)
423 m.next = "FETCH_PRED_DONE"
424
425 with m.State("FETCH_PRED_DONE"):
426 comb += pred_mask_valid_o.eq(1)
427 with m.If(pred_mask_ready_i):
428 m.next = "FETCH_PRED_IDLE"
429
430 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
431 dbg, core_rst, is_svp64_mode,
432 fetch_pc_ready_o, fetch_pc_valid_i,
433 fetch_insn_valid_o, fetch_insn_ready_i,
434 pred_insn_valid_i, pred_insn_ready_o,
435 pred_mask_valid_o, pred_mask_ready_i,
436 exec_insn_valid_i, exec_insn_ready_o,
437 exec_pc_valid_o, exec_pc_ready_i):
438 """issue FSM
439
440 decode / issue FSM. this interacts with the "fetch" FSM
441 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
442 (outgoing). also interacts with the "execute" FSM
443 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
444 (incoming).
445 SVP64 RM prefixes have already been set up by the
446 "fetch" phase, so execute is fairly straightforward.
447 """
448
449 comb = m.d.comb
450 sync = m.d.sync
451 pdecode2 = self.pdecode2
452 cur_state = self.cur_state
453
454 # temporaries
455 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
456
457 # for updating svstate (things like srcstep etc.)
458 update_svstate = Signal() # set this (below) if updating
459 new_svstate = SVSTATERec("new_svstate")
460 comb += new_svstate.eq(cur_state.svstate)
461
462 # precalculate srcstep+1 and dststep+1
463 cur_srcstep = cur_state.svstate.srcstep
464 cur_dststep = cur_state.svstate.dststep
465 next_srcstep = Signal.like(cur_srcstep)
466 next_dststep = Signal.like(cur_dststep)
467 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
468 comb += next_dststep.eq(cur_state.svstate.dststep+1)
469
470 with m.FSM(name="issue_fsm"):
471
472 # sync with the "fetch" phase which is reading the instruction
473 # at this point, there is no instruction running, that
474 # could inadvertently update the PC.
475 with m.State("ISSUE_START"):
476 # wait on "core stop" release, before next fetch
477 # need to do this here, in case we are in a VL==0 loop
478 with m.If(~dbg.core_stop_o & ~core_rst):
479 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
480 with m.If(fetch_pc_ready_o): # fetch acknowledged us
481 m.next = "INSN_WAIT"
482 with m.Else():
483 # tell core it's stopped, and acknowledge debug handshake
484 comb += core.core_stopped_i.eq(1)
485 comb += dbg.core_stopped_i.eq(1)
486 # while stopped, allow updating the PC and SVSTATE
487 with m.If(self.pc_i.ok):
488 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
489 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
490 sync += pc_changed.eq(1)
491 with m.If(self.svstate_i.ok):
492 comb += new_svstate.eq(self.svstate_i.data)
493 comb += update_svstate.eq(1)
494 sync += sv_changed.eq(1)
495
496 # decode the instruction when it arrives
497 with m.State("INSN_WAIT"):
498 comb += fetch_insn_ready_i.eq(1)
499 with m.If(fetch_insn_valid_o):
500 # decode the instruction
501 sync += core.e.eq(pdecode2.e)
502 sync += core.state.eq(cur_state)
503 sync += core.raw_insn_i.eq(dec_opcode_i)
504 sync += core.bigendian_i.eq(self.core_bigendian_i)
505 # set RA_OR_ZERO detection in satellite decoders
506 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
507 # loop into ISSUE_START if it's a SVP64 instruction
508 # and VL == 0. this because VL==0 is a for-loop
509 # from 0 to 0 i.e. always, always a NOP.
510 cur_vl = cur_state.svstate.vl
511 with m.If(is_svp64_mode & (cur_vl == 0)):
512 # update the PC before fetching the next instruction
513 # since we are in a VL==0 loop, no instruction was
514 # executed that we could be overwriting
515 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
516 comb += self.state_w_pc.data_i.eq(nia)
517 comb += self.insn_done.eq(1)
518 m.next = "ISSUE_START"
519 with m.Else():
520 m.next = "PRED_START" # start fetching the predicate
521
522 with m.State("PRED_START"):
523 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
524 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
525 m.next = "MASK_WAIT"
526
527 with m.State("MASK_WAIT"):
528 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
529 with m.If(pred_mask_valid_o): # predication masks are ready
530 m.next = "INSN_EXECUTE"
531
532 # handshake with execution FSM, move to "wait" once acknowledged
533 with m.State("INSN_EXECUTE"):
534 # with m.If(is_svp64_mode):
535 # TODO advance src/dst step to "skip" over predicated-out
536 # from self.srcmask and self.dstmask
537 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
538 # but still without exceeding VL in either case
539 # IMPORTANT: when changing src/dest step, have to
540 # jump to m.next = "DECODE_SV" to deal with the change in
541 # SVSTATE
542
543 with m.If(is_svp64_mode):
544
545 pred_src_zero = pdecode2.rm_dec.pred_sz
546 pred_dst_zero = pdecode2.rm_dec.pred_dz
547
548 """
549 if not pred_src_zero:
550 if (((1<<cur_srcstep) & self.srcmask) == 0) and
551 (cur_srcstep != vl):
552 comb += update_svstate.eq(1)
553 comb += new_svstate.srcstep.eq(next_srcstep)
554 sync += sv_changed.eq(1)
555
556 if not pred_dst_zero:
557 if (((1<<cur_dststep) & self.dstmask) == 0) and
558 (cur_dststep != vl):
559 comb += new_svstate.dststep.eq(next_dststep)
560 comb += update_svstate.eq(1)
561 sync += sv_changed.eq(1)
562
563 if update_svstate:
564 m.next = "DECODE_SV"
565 """
566
567 comb += exec_insn_valid_i.eq(1) # trigger execute
568 with m.If(exec_insn_ready_o): # execute acknowledged us
569 m.next = "EXECUTE_WAIT"
570
571 with m.State("EXECUTE_WAIT"):
572 # wait on "core stop" release, at instruction end
573 # need to do this here, in case we are in a VL>1 loop
574 with m.If(~dbg.core_stop_o & ~core_rst):
575 comb += exec_pc_ready_i.eq(1)
576 with m.If(exec_pc_valid_o):
577
578 # was this the last loop iteration?
579 is_last = Signal()
580 cur_vl = cur_state.svstate.vl
581 comb += is_last.eq(next_srcstep == cur_vl)
582
583 # if either PC or SVSTATE were changed by the previous
584 # instruction, go directly back to Fetch, without
585 # updating either PC or SVSTATE
586 with m.If(pc_changed | sv_changed):
587 m.next = "ISSUE_START"
588
589 # also return to Fetch, when no output was a vector
590 # (regardless of SRCSTEP and VL), or when the last
591 # instruction was really the last one of the VL loop
592 with m.Elif((~pdecode2.loop_continue) | is_last):
593 # before going back to fetch, update the PC state
594 # register with the NIA.
595 # ok here we are not reading the branch unit.
596 # TODO: this just blithely overwrites whatever
597 # pipeline updated the PC
598 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
599 comb += self.state_w_pc.data_i.eq(nia)
600 # reset SRCSTEP before returning to Fetch
601 with m.If(pdecode2.loop_continue):
602 comb += new_svstate.srcstep.eq(0)
603 comb += new_svstate.dststep.eq(0)
604 comb += update_svstate.eq(1)
605 m.next = "ISSUE_START"
606
607 # returning to Execute? then, first update SRCSTEP
608 with m.Else():
609 comb += new_svstate.srcstep.eq(next_srcstep)
610 comb += new_svstate.dststep.eq(next_dststep)
611 comb += update_svstate.eq(1)
612 m.next = "DECODE_SV"
613
614 with m.Else():
615 comb += core.core_stopped_i.eq(1)
616 comb += dbg.core_stopped_i.eq(1)
617 # while stopped, allow updating the PC and SVSTATE
618 with m.If(self.pc_i.ok):
619 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
620 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
621 sync += pc_changed.eq(1)
622 with m.If(self.svstate_i.ok):
623 comb += new_svstate.eq(self.svstate_i.data)
624 comb += update_svstate.eq(1)
625 sync += sv_changed.eq(1)
626
627 # need to decode the instruction again, after updating SRCSTEP
628 # in the previous state.
629 # mostly a copy of INSN_WAIT, but without the actual wait
630 with m.State("DECODE_SV"):
631 # decode the instruction
632 sync += core.e.eq(pdecode2.e)
633 sync += core.state.eq(cur_state)
634 sync += core.bigendian_i.eq(self.core_bigendian_i)
635 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
636 m.next = "INSN_EXECUTE" # move to "execute"
637
638 # check if svstate needs updating: if so, write it to State Regfile
639 with m.If(update_svstate):
640 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
641 comb += self.state_w_sv.data_i.eq(new_svstate)
642 sync += cur_state.svstate.eq(new_svstate) # for next clock
643
644 def execute_fsm(self, m, core, pc_changed, sv_changed,
645 exec_insn_valid_i, exec_insn_ready_o,
646 exec_pc_valid_o, exec_pc_ready_i):
647 """execute FSM
648
649 execute FSM. this interacts with the "issue" FSM
650 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
651 (outgoing). SVP64 RM prefixes have already been set up by the
652 "issue" phase, so execute is fairly straightforward.
653 """
654
655 comb = m.d.comb
656 sync = m.d.sync
657 pdecode2 = self.pdecode2
658
659 # temporaries
660 core_busy_o = core.busy_o # core is busy
661 core_ivalid_i = core.ivalid_i # instruction is valid
662 core_issue_i = core.issue_i # instruction is issued
663 insn_type = core.e.do.insn_type # instruction MicroOp type
664
665 with m.FSM(name="exec_fsm"):
666
667 # waiting for instruction bus (stays there until not busy)
668 with m.State("INSN_START"):
669 comb += exec_insn_ready_o.eq(1)
670 with m.If(exec_insn_valid_i):
671 comb += core_ivalid_i.eq(1) # instruction is valid
672 comb += core_issue_i.eq(1) # and issued
673 sync += sv_changed.eq(0)
674 sync += pc_changed.eq(0)
675 m.next = "INSN_ACTIVE" # move to "wait completion"
676
677 # instruction started: must wait till it finishes
678 with m.State("INSN_ACTIVE"):
679 with m.If(insn_type != MicrOp.OP_NOP):
680 comb += core_ivalid_i.eq(1) # instruction is valid
681 # note changes to PC and SVSTATE
682 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
683 sync += sv_changed.eq(1)
684 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
685 sync += pc_changed.eq(1)
686 with m.If(~core_busy_o): # instruction done!
687 comb += exec_pc_valid_o.eq(1)
688 with m.If(exec_pc_ready_i):
689 comb += self.insn_done.eq(1)
690 m.next = "INSN_START" # back to fetch
691
692 def setup_peripherals(self, m):
693 comb, sync = m.d.comb, m.d.sync
694
695 m.submodules.core = core = DomainRenamer("coresync")(self.core)
696 m.submodules.imem = imem = self.imem
697 m.submodules.dbg = dbg = self.dbg
698 if self.jtag_en:
699 m.submodules.jtag = jtag = self.jtag
700 # TODO: UART2GDB mux, here, from external pin
701 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
702 sync += dbg.dmi.connect_to(jtag.dmi)
703
704 cur_state = self.cur_state
705
706 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
707 if self.sram4x4k:
708 for i, sram in enumerate(self.sram4k):
709 m.submodules["sram4k_%d" % i] = sram
710 comb += sram.enable.eq(self.wb_sram_en)
711
712 # XICS interrupt handler
713 if self.xics:
714 m.submodules.xics_icp = icp = self.xics_icp
715 m.submodules.xics_ics = ics = self.xics_ics
716 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
717 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
718
719 # GPIO test peripheral
720 if self.gpio:
721 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
722
723 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
724 # XXX causes litex ECP5 test to get wrong idea about input and output
725 # (but works with verilator sim *sigh*)
726 #if self.gpio and self.xics:
727 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
728
729 # instruction decoder
730 pdecode = create_pdecode()
731 m.submodules.dec2 = pdecode2 = self.pdecode2
732 if self.svp64_en:
733 m.submodules.svp64 = svp64 = self.svp64
734
735 # convenience
736 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
737 intrf = self.core.regs.rf['int']
738
739 # clock delay power-on reset
740 cd_por = ClockDomain(reset_less=True)
741 cd_sync = ClockDomain()
742 core_sync = ClockDomain("coresync")
743 m.domains += cd_por, cd_sync, core_sync
744
745 ti_rst = Signal(reset_less=True)
746 delay = Signal(range(4), reset=3)
747 with m.If(delay != 0):
748 m.d.por += delay.eq(delay - 1)
749 comb += cd_por.clk.eq(ClockSignal())
750
751 # power-on reset delay
752 core_rst = ResetSignal("coresync")
753 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
754 comb += core_rst.eq(ti_rst)
755
756 # busy/halted signals from core
757 comb += self.busy_o.eq(core.busy_o)
758 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
759
760 # temporary hack: says "go" immediately for both address gen and ST
761 l0 = core.l0
762 ldst = core.fus.fus['ldst0']
763 st_go_edge = rising_edge(m, ldst.st.rel_o)
764 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
765 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
766
767 return core_rst
768
769 def elaborate(self, platform):
770 m = Module()
771 # convenience
772 comb, sync = m.d.comb, m.d.sync
773 cur_state = self.cur_state
774 pdecode2 = self.pdecode2
775 dbg = self.dbg
776 core = self.core
777
778 # set up peripherals and core
779 core_rst = self.setup_peripherals(m)
780
781 # PC and instruction from I-Memory
782 comb += self.pc_o.eq(cur_state.pc)
783 pc_changed = Signal() # note write to PC
784 sv_changed = Signal() # note write to SVSTATE
785
786 # read state either from incoming override or from regfile
787 # TODO: really should be doing MSR in the same way
788 pc = state_get(m, self.pc_i, "pc", # read PC
789 self.state_r_pc, StateRegs.PC)
790 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
791 self.state_r_sv, StateRegs.SVSTATE)
792
793 # don't write pc every cycle
794 comb += self.state_w_pc.wen.eq(0)
795 comb += self.state_w_pc.data_i.eq(0)
796
797 # don't read msr every cycle
798 comb += self.state_r_msr.ren.eq(0)
799
800 # address of the next instruction, in the absence of a branch
801 # depends on the instruction size
802 nia = Signal(64, reset_less=True)
803
804 # connect up debug signals
805 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
806 comb += dbg.terminate_i.eq(core.core_terminate_o)
807 comb += dbg.state.pc.eq(pc)
808 comb += dbg.state.svstate.eq(svstate)
809 comb += dbg.state.msr.eq(cur_state.msr)
810
811 # pass the prefix mode from Fetch to Issue, so the latter can loop
812 # on VL==0
813 is_svp64_mode = Signal()
814
815 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
816 # these are the handshake signals between fetch and decode/execute
817
818 # fetch FSM can run as soon as the PC is valid
819 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
820 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
821
822 # fetch FSM hands over the instruction to be decoded / issued
823 fetch_insn_valid_o = Signal()
824 fetch_insn_ready_i = Signal()
825
826 # predicate fetch FSM decodes and fetches the predicate
827 pred_insn_valid_i = Signal()
828 pred_insn_ready_o = Signal()
829
830 # predicate fetch FSM delivers the masks
831 pred_mask_valid_o = Signal()
832 pred_mask_ready_i = Signal()
833
834 # issue FSM delivers the instruction to the be executed
835 exec_insn_valid_i = Signal()
836 exec_insn_ready_o = Signal()
837
838 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
839 exec_pc_valid_o = Signal()
840 exec_pc_ready_i = Signal()
841
842 # the FSMs here are perhaps unusual in that they detect conditions
843 # then "hold" information, combinatorially, for the core
844 # (as opposed to using sync - which would be on a clock's delay)
845 # this includes the actual opcode, valid flags and so on.
846
847 # Fetch, then predicate fetch, then Issue, then Execute.
848 # Issue is where the VL for-loop # lives. the ready/valid
849 # signalling is used to communicate between the four.
850
851 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
852 fetch_pc_ready_o, fetch_pc_valid_i,
853 fetch_insn_valid_o, fetch_insn_ready_i)
854
855 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
856 dbg, core_rst, is_svp64_mode,
857 fetch_pc_ready_o, fetch_pc_valid_i,
858 fetch_insn_valid_o, fetch_insn_ready_i,
859 pred_insn_valid_i, pred_insn_ready_o,
860 pred_mask_valid_o, pred_mask_ready_i,
861 exec_insn_valid_i, exec_insn_ready_o,
862 exec_pc_valid_o, exec_pc_ready_i)
863
864 self.fetch_predicate_fsm(m,
865 pred_insn_valid_i, pred_insn_ready_o,
866 pred_mask_valid_o, pred_mask_ready_i)
867
868 self.execute_fsm(m, core, pc_changed, sv_changed,
869 exec_insn_valid_i, exec_insn_ready_o,
870 exec_pc_valid_o, exec_pc_ready_i)
871
872 # this bit doesn't have to be in the FSM: connect up to read
873 # regfiles on demand from DMI
874 self.do_dmi(m, dbg)
875
876 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
877 # (which uses that in PowerDecoder2 to raise 0x900 exception)
878 self.tb_dec_fsm(m, cur_state.dec)
879
880 return m
881
882 def do_dmi(self, m, dbg):
883 """deals with DMI debug requests
884
885 currently only provides read requests for the INT regfile, CR and XER
886 it will later also deal with *writing* to these regfiles.
887 """
888 comb = m.d.comb
889 sync = m.d.sync
890 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
891 intrf = self.core.regs.rf['int']
892
893 with m.If(d_reg.req): # request for regfile access being made
894 # TODO: error-check this
895 # XXX should this be combinatorial? sync better?
896 if intrf.unary:
897 comb += self.int_r.ren.eq(1<<d_reg.addr)
898 else:
899 comb += self.int_r.addr.eq(d_reg.addr)
900 comb += self.int_r.ren.eq(1)
901 d_reg_delay = Signal()
902 sync += d_reg_delay.eq(d_reg.req)
903 with m.If(d_reg_delay):
904 # data arrives one clock later
905 comb += d_reg.data.eq(self.int_r.data_o)
906 comb += d_reg.ack.eq(1)
907
908 # sigh same thing for CR debug
909 with m.If(d_cr.req): # request for regfile access being made
910 comb += self.cr_r.ren.eq(0b11111111) # enable all
911 d_cr_delay = Signal()
912 sync += d_cr_delay.eq(d_cr.req)
913 with m.If(d_cr_delay):
914 # data arrives one clock later
915 comb += d_cr.data.eq(self.cr_r.data_o)
916 comb += d_cr.ack.eq(1)
917
918 # aaand XER...
919 with m.If(d_xer.req): # request for regfile access being made
920 comb += self.xer_r.ren.eq(0b111111) # enable all
921 d_xer_delay = Signal()
922 sync += d_xer_delay.eq(d_xer.req)
923 with m.If(d_xer_delay):
924 # data arrives one clock later
925 comb += d_xer.data.eq(self.xer_r.data_o)
926 comb += d_xer.ack.eq(1)
927
928 def tb_dec_fsm(self, m, spr_dec):
929 """tb_dec_fsm
930
931 this is a FSM for updating either dec or tb. it runs alternately
932 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
933 value to DEC, however the regfile has "passthrough" on it so this
934 *should* be ok.
935
936 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
937 """
938
939 comb, sync = m.d.comb, m.d.sync
940 fast_rf = self.core.regs.rf['fast']
941 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
942 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
943
944 with m.FSM() as fsm:
945
946 # initiates read of current DEC
947 with m.State("DEC_READ"):
948 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
949 comb += fast_r_dectb.ren.eq(1)
950 m.next = "DEC_WRITE"
951
952 # waits for DEC read to arrive (1 cycle), updates with new value
953 with m.State("DEC_WRITE"):
954 new_dec = Signal(64)
955 # TODO: MSR.LPCR 32-bit decrement mode
956 comb += new_dec.eq(fast_r_dectb.data_o - 1)
957 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
958 comb += fast_w_dectb.wen.eq(1)
959 comb += fast_w_dectb.data_i.eq(new_dec)
960 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
961 m.next = "TB_READ"
962
963 # initiates read of current TB
964 with m.State("TB_READ"):
965 comb += fast_r_dectb.addr.eq(FastRegs.TB)
966 comb += fast_r_dectb.ren.eq(1)
967 m.next = "TB_WRITE"
968
969 # waits for read TB to arrive, initiates write of current TB
970 with m.State("TB_WRITE"):
971 new_tb = Signal(64)
972 comb += new_tb.eq(fast_r_dectb.data_o + 1)
973 comb += fast_w_dectb.addr.eq(FastRegs.TB)
974 comb += fast_w_dectb.wen.eq(1)
975 comb += fast_w_dectb.data_i.eq(new_tb)
976 m.next = "DEC_READ"
977
978 return m
979
980 def __iter__(self):
981 yield from self.pc_i.ports()
982 yield self.pc_o
983 yield self.memerr_o
984 yield from self.core.ports()
985 yield from self.imem.ports()
986 yield self.core_bigendian_i
987 yield self.busy_o
988
989 def ports(self):
990 return list(self)
991
992 def external_ports(self):
993 ports = self.pc_i.ports()
994 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
995 ]
996
997 if self.jtag_en:
998 ports += list(self.jtag.external_ports())
999 else:
1000 # don't add DMI if JTAG is enabled
1001 ports += list(self.dbg.dmi.ports())
1002
1003 ports += list(self.imem.ibus.fields.values())
1004 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1005
1006 if self.sram4x4k:
1007 for sram in self.sram4k:
1008 ports += list(sram.bus.fields.values())
1009
1010 if self.xics:
1011 ports += list(self.xics_icp.bus.fields.values())
1012 ports += list(self.xics_ics.bus.fields.values())
1013 ports.append(self.int_level_i)
1014
1015 if self.gpio:
1016 ports += list(self.simple_gpio.bus.fields.values())
1017 ports.append(self.gpio_o)
1018
1019 return ports
1020
1021 def ports(self):
1022 return list(self)
1023
1024
1025 class TestIssuer(Elaboratable):
1026 def __init__(self, pspec):
1027 self.ti = TestIssuerInternal(pspec)
1028
1029 self.pll = DummyPLL()
1030
1031 # PLL direct clock or not
1032 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1033 if self.pll_en:
1034 self.pll_18_o = Signal(reset_less=True)
1035
1036 def elaborate(self, platform):
1037 m = Module()
1038 comb = m.d.comb
1039
1040 # TestIssuer runs at direct clock
1041 m.submodules.ti = ti = self.ti
1042 cd_int = ClockDomain("coresync")
1043
1044 if self.pll_en:
1045 # ClockSelect runs at PLL output internal clock rate
1046 m.submodules.pll = pll = self.pll
1047
1048 # add clock domains from PLL
1049 cd_pll = ClockDomain("pllclk")
1050 m.domains += cd_pll
1051
1052 # PLL clock established. has the side-effect of running clklsel
1053 # at the PLL's speed (see DomainRenamer("pllclk") above)
1054 pllclk = ClockSignal("pllclk")
1055 comb += pllclk.eq(pll.clk_pll_o)
1056
1057 # wire up external 24mhz to PLL
1058 comb += pll.clk_24_i.eq(ClockSignal())
1059
1060 # output 18 mhz PLL test signal
1061 comb += self.pll_18_o.eq(pll.pll_18_o)
1062
1063 # now wire up ResetSignals. don't mind them being in this domain
1064 pll_rst = ResetSignal("pllclk")
1065 comb += pll_rst.eq(ResetSignal())
1066
1067 # internal clock is set to selector clock-out. has the side-effect of
1068 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1069 intclk = ClockSignal("coresync")
1070 if self.pll_en:
1071 comb += intclk.eq(pll.clk_pll_o)
1072 else:
1073 comb += intclk.eq(ClockSignal())
1074
1075 return m
1076
1077 def ports(self):
1078 return list(self.ti.ports()) + list(self.pll.ports()) + \
1079 [ClockSignal(), ResetSignal()]
1080
1081 def external_ports(self):
1082 ports = self.ti.external_ports()
1083 ports.append(ClockSignal())
1084 ports.append(ResetSignal())
1085 if self.pll_en:
1086 ports.append(self.pll.clk_sel_i)
1087 ports.append(self.pll_18_o)
1088 ports.append(self.pll.pll_lck_o)
1089 return ports
1090
1091
1092 if __name__ == '__main__':
1093 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1094 'spr': 1,
1095 'div': 1,
1096 'mul': 1,
1097 'shiftrot': 1
1098 }
1099 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1100 imem_ifacetype='bare_wb',
1101 addr_wid=48,
1102 mask_wid=8,
1103 reg_wid=64,
1104 units=units)
1105 dut = TestIssuer(pspec)
1106 vl = main(dut, ports=dut.ports(), name="test_issuer")
1107
1108 if len(sys.argv) == 1:
1109 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1110 with open("test_issuer.il", "w") as f:
1111 f.write(vl)