src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20
  21
  22 from soc.decoder.decode2execute1 import Data
  23 from soc.experiment.testmem import TestMemory # test only for instructions
  24 from soc.regfile.regfiles import FastRegs
  25 from soc.simple.core import NonProductionCore
  26
  27
  28 class TestIssuer(Elaboratable):
  29     """TestIssuer - reads instructions from TestMemory and issues them
  30
  31     efficiency and speed is not the main goal here: functional correctness is.
  32     """
  33     def __init__(self, addrwid=6, idepth=6):
  34         # main instruction core
  35         self.core = core = NonProductionCore(addrwid)
  36
  37         # Test Instruction memory
  38         self.imem = TestMemory(32, idepth)
  39         self.i_rd = self.imem.rdport
  40         #self.i_wr = self.imem.write_port() errr...
  41
  42         # instruction go/monitor
  43         self.go_insn_i = Signal(reset_less=True)
  44         self.pc_o = Signal(64, reset_less=True)
  45         self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
  46         self.busy_o = core.busy_o
  47         self.memerr_o = Signal(reset_less=True)
  48
  49         # FAST regfile read /write ports
  50         self.fast_rd1 = self.core.regs.rf['fast'].r_ports['d_rd1']
  51         self.fast_wr1 = self.core.regs.rf['fast'].w_ports['d_wr1']
  52         # hack method of keeping an eye on whether branch/trap set the PC
  53         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  54
  55     def elaborate(self, platform):
  56         m = Module()
  57         comb, sync = m.d.comb, m.d.sync
  58
  59         m.submodules.core = core = self.core
  60         m.submodules.imem = imem = self.imem
  61
  62         # temporary hack: says "go" immediately for both address gen and ST
  63         l0 = core.l0
  64         ldst = core.fus.fus['ldst0']
  65         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  66         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  67
  68         # PC and instruction from I-Memory
  69         current_insn = Signal(32) # current fetched instruction (note sync)
  70         current_pc = Signal(64) # current PC (note it is reset/sync)
  71         pc_changed = Signal(64) # note write to PC
  72         comb += self.pc_o.eq(current_pc)
  73         ilatch = Signal(32)
  74
  75         # next instruction (+4 on current)
  76         nia = Signal(64, reset_less=True)
  77         comb += nia.eq(current_pc + 4)
  78
  79         # temporaries
  80         core_busy_o = core.busy_o         # core is busy
  81         core_ivalid_i = core.ivalid_i     # instruction is valid
  82         core_issue_i = core.issue_i       # instruction is issued
  83         core_be_i = core.bigendian_i      # bigendian mode
  84         core_opcode_i = core.raw_opcode_i # raw opcode
  85
  86         # actually use a nmigen FSM for the first time (w00t)
  87         with m.FSM() as fsm:
  88
  89             # waiting (zzz)
  90             with m.State("IDLE"):
  91                 sync += pc_changed.eq(0)
  92                 with m.If(self.go_insn_i):
  93                     # instruction allowed to go: start by reading the PC
  94                     pc = Signal(64, reset_less=True)
  95                     with m.If(self.pc_i.ok):
  96                         # incoming override (start from pc_i)
  97                         comb += pc.eq(self.pc_i.data)
  98                     with m.Else():
  99                         # otherwise read FastRegs regfile for PC
 100                         comb += self.fast_rd1.ren.eq(1<<FastRegs.PC)
 101                         comb += pc.eq(self.fast_rd1.data_o)
 102                     # capture the PC and also drop it into Insn Memory
 103                     # we have joined a pair of combinatorial memory
 104                     # lookups together.  this is Generally Bad.
 105                     comb += self.i_rd.addr.eq(pc[2:]) # ignore last 2 bits
 106                     comb += current_insn.eq(self.i_rd.data)
 107                     comb += current_pc.eq(pc)
 108                     m.next = "INSN_READ" # move to "issue" phase
 109
 110             # got the instruction: start issue
 111             with m.State("INSN_READ"):
 112                 comb += current_insn.eq(self.i_rd.data)
 113                 comb += core_ivalid_i.eq(1) # say instruction is valid
 114                 comb += core_issue_i.eq(1)  # and issued (ivalid_i redundant)
 115                 comb += core_be_i.eq(0)     # little-endian mode
 116                 comb += core_opcode_i.eq(current_insn) # actual opcode
 117                 sync += ilatch.eq(current_insn)
 118                 m.next = "INSN_ACTIVE" # move to "wait for completion" phase
 119
 120             # instruction started: must wait till it finishes
 121             with m.State("INSN_ACTIVE"):
 122                 comb += core_ivalid_i.eq(1) # say instruction is valid
 123                 comb += core_opcode_i.eq(ilatch) # actual opcode
 124                 #sync += core_issue_i.eq(0) # issue raises for only one cycle
 125                 with m.If(self.fast_nia.wen):
 126                     sync += pc_changed.eq(1)
 127                 with m.If(~core_busy_o): # instruction done!
 128                     #sync += core_ivalid_i.eq(0) # say instruction is invalid
 129                     #sync += core_opcode_i.eq(0) # clear out (no good reason)
 130                     # ok here we are not reading the branch unit.  TODO
 131                     # this just blithely overwrites whatever pipeline updated
 132                     # the PC
 133                     with m.If(~self.fast_nia.wen & ~pc_changed):
 134                         comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
 135                         comb += self.fast_wr1.data_i.eq(nia)
 136                     m.next = "IDLE" # back to idle
 137
 138         return m
 139
 140     def __iter__(self):
 141         yield from self.pc_i.ports()
 142         yield self.pc_o
 143         yield self.go_insn_i
 144         yield self.memerr_o
 145         yield from self.core.ports()
 146         yield from self.imem.ports()
 147
 148     def ports(self):
 149         return list(self)
 150
 151
 152 if __name__ == '__main__':
 153     dut = TestIssuer()
 154     vl = rtlil.convert(dut, ports=dut.ports())
 155     with open("test_issuer.il", "w") as f:
 156         f.write(vl)
 157