src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import FastRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32 from soc.config.state import CoreState
  33
  34
  35 class TestIssuer(Elaboratable):
  36     """TestIssuer - reads instructions from TestMemory and issues them
  37
  38     efficiency and speed is not the main goal here: functional correctness is.
  39     """
  40     def __init__(self, pspec):
  41         # main instruction core
  42         self.core = core = NonProductionCore(pspec)
  43
  44         # Test Instruction memory
  45         self.imem = ConfigFetchUnit(pspec).fu
  46         # one-row cache of instruction read
  47         self.iline = Signal(64) # one instruction line
  48         self.iprev_adr = Signal(64) # previous address: if different, do read
  49
  50         # DMI interface
  51         self.dbg = CoreDebug()
  52
  53         # instruction go/monitor
  54         self.pc_o = Signal(64, reset_less=True)
  55         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  56         self.core_bigendian_i = Signal()
  57         self.busy_o = Signal(reset_less=True)
  58         self.memerr_o = Signal(reset_less=True)
  59
  60         # FAST regfile read /write ports for PC and MSR
  61         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
  62         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  63         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
  64
  65         # DMI interface access
  66         self.int_r = self.core.regs.rf['int'].r_ports['dmi'] # INT read
  67
  68         # hack method of keeping an eye on whether branch/trap set the PC
  69         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  70         self.fast_nia.wen.name = 'fast_nia_wen'
  71
  72     def elaborate(self, platform):
  73         m = Module()
  74         comb, sync = m.d.comb, m.d.sync
  75
  76         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  77         m.submodules.imem = imem = self.imem
  78         m.submodules.dbg = dbg = self.dbg
  79
  80         # convenience
  81         dmi = dbg.dmi
  82         d_reg = dbg.dbg_gpr
  83
  84         # clock delay power-on reset
  85         cd_por  = ClockDomain(reset_less=True)
  86         cd_sync = ClockDomain()
  87         core_sync = ClockDomain("coresync")
  88         m.domains += cd_por, cd_sync, core_sync
  89
  90         delay = Signal(range(4), reset=1)
  91         with m.If(delay != 0):
  92             m.d.por += delay.eq(delay - 1)
  93         comb += cd_por.clk.eq(ClockSignal())
  94         comb += core_sync.clk.eq(ClockSignal())
  95         # XXX TODO: power-on reset delay (later)
  96         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
  97
  98         # busy/halted signals from core
  99         comb += self.busy_o.eq(core.busy_o)
 100         comb += core.bigendian_i.eq(self.core_bigendian_i)
 101
 102         # current state (MSR/PC at the moment
 103         cur_state = CoreState("cur")
 104
 105         # temporary hack: says "go" immediately for both address gen and ST
 106         l0 = core.l0
 107         ldst = core.fus.fus['ldst0']
 108         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 109         m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 110
 111         # PC and instruction from I-Memory
 112         current_insn = Signal(32) # current fetched instruction (note sync)
 113         pc_changed = Signal() # note write to PC
 114         comb += self.pc_o.eq(cur_state.pc)
 115         ilatch = Signal(32)
 116
 117         # MSR
 118         msr = Signal(64, reset_less=True)
 119
 120         # next instruction (+4 on current)
 121         nia = Signal(64, reset_less=True)
 122         comb += nia.eq(cur_state.pc + 4)
 123
 124         # read the PC
 125         pc = Signal(64, reset_less=True)
 126         with m.If(self.pc_i.ok):
 127             # incoming override (start from pc_i)
 128             comb += pc.eq(self.pc_i.data)
 129         with m.Else():
 130             # otherwise read FastRegs regfile for PC
 131             comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 132             comb += pc.eq(self.fast_r_pc.data_o)
 133
 134         # connect up debug signals
 135         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 136         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 137         comb += core.core_reset_i.eq(dbg.core_rst_o)
 138         comb += dbg.terminate_i.eq(core.core_terminate_o)
 139         comb += dbg.state.pc.eq(pc)
 140         comb += dbg.state.msr.eq(cur_state.msr)
 141
 142         # temporaries
 143         core_busy_o = core.busy_o         # core is busy
 144         core_ivalid_i = core.ivalid_i     # instruction is valid
 145         core_issue_i = core.issue_i       # instruction is issued
 146         core_be_i = core.bigendian_i      # bigendian mode
 147         core_opcode_i = core.raw_opcode_i # raw opcode
 148
 149         insn_type = core.pdecode2.e.do.insn_type
 150         insn_state = core.pdecode2.state
 151
 152         # actually use a nmigen FSM for the first time (w00t)
 153         # this FSM is perhaps unusual in that it detects conditions
 154         # then "holds" information, combinatorially, for the core
 155         # (as opposed to using sync - which would be on a clock's delay)
 156         # this includes the actual opcode, valid flags and so on.
 157         with m.FSM() as fsm:
 158
 159             # waiting (zzz)
 160             with m.State("IDLE"):
 161                 sync += pc_changed.eq(0)
 162                 with m.If(~dbg.core_stop_o):
 163                     # instruction allowed to go: start by reading the PC
 164                     # capture the PC and also drop it into Insn Memory
 165                     # we have joined a pair of combinatorial memory
 166                     # lookups together.  this is Generally Bad.
 167                     comb += self.imem.a_pc_i.eq(pc)
 168                     comb += self.imem.a_valid_i.eq(1)
 169                     comb += self.imem.f_valid_i.eq(1)
 170                     sync += cur_state.pc.eq(pc)
 171                     m.next = "INSN_READ" # move to "wait for bus" phase
 172
 173             # waiting for instruction bus (stays there until not busy)
 174             with m.State("INSN_READ"):
 175                 with m.If(self.imem.f_busy_o): # zzz...
 176                     # busy: stay in wait-read
 177                     comb += self.imem.a_valid_i.eq(1)
 178                     comb += self.imem.f_valid_i.eq(1)
 179                 with m.Else():
 180                     # not busy: instruction fetched
 181                     f_instr_o = self.imem.f_instr_o
 182                     if f_instr_o.width == 32:
 183                         insn = f_instr_o
 184                     else:
 185                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 186                     comb += current_insn.eq(insn)
 187                     comb += core_ivalid_i.eq(1) # instruction is valid
 188                     comb += core_issue_i.eq(1)  # and issued
 189                     comb += core_opcode_i.eq(current_insn) # actual opcode
 190                     sync += ilatch.eq(current_insn) # latch current insn
 191
 192                     # read MSR, latch it, and put it in decode "state"
 193                     comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 194                     comb += msr.eq(self.fast_r_msr.data_o)
 195                     comb += insn_state.msr.eq(msr)
 196                     sync += cur_state.msr.eq(msr) # latch current MSR
 197
 198                     # also drop PC into decode "state"
 199                     comb += insn_state.pc.eq(cur_state.pc)
 200
 201                     m.next = "INSN_ACTIVE" # move to "wait completion"
 202
 203             # instruction started: must wait till it finishes
 204             with m.State("INSN_ACTIVE"):
 205                 with m.If(insn_type != MicrOp.OP_NOP):
 206                     comb += core_ivalid_i.eq(1) # instruction is valid
 207                 comb += core_opcode_i.eq(ilatch) # actual opcode
 208                 comb += insn_state.eq(cur_state)     # and MSR and PC
 209                 with m.If(self.fast_nia.wen):
 210                     sync += pc_changed.eq(1)
 211                 with m.If(~core_busy_o): # instruction done!
 212                     # ok here we are not reading the branch unit.  TODO
 213                     # this just blithely overwrites whatever pipeline
 214                     # updated the PC
 215                     with m.If(~pc_changed):
 216                         comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 217                         comb += self.fast_w_pc.data_i.eq(nia)
 218                     m.next = "IDLE" # back to idle
 219
 220         # this bit doesn't have to be in the FSM: connect up to read
 221         # regfiles on demand from DMI
 222
 223         with m.If(d_reg.req): # request for regfile access being made
 224             # TODO: error-check this
 225             # XXX should this be combinatorial?  sync better?
 226             comb += self.int_r.ren.eq(1<<d_reg.addr)
 227             comb += d_reg.data.eq(self.int_r.data_o)
 228             comb += d_reg.ack.eq(1)
 229
 230         return m
 231
 232     def __iter__(self):
 233         yield from self.pc_i.ports()
 234         yield self.pc_o
 235         yield self.memerr_o
 236         yield from self.core.ports()
 237         yield from self.imem.ports()
 238         yield self.core_bigendian_i
 239         yield self.busy_o
 240
 241     def ports(self):
 242         return list(self)
 243
 244     def external_ports(self):
 245         return self.pc_i.ports() + [self.pc_o,
 246                                     self.memerr_o,
 247                                     self.core_bigendian_i,
 248                                     ClockSignal(),
 249                                     ResetSignal(),
 250                                     self.busy_o,
 251                                     ] + \
 252                 list(self.dbg.dmi.ports()) + \
 253                 list(self.imem.ibus.fields.values()) + \
 254                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 255
 256     def ports(self):
 257         return list(self)
 258
 259
 260 if __name__ == '__main__':
 261     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 262              'spr': 1,
 263              'mul': 1,
 264              'shiftrot': 1}
 265     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 266                          imem_ifacetype='bare_wb',
 267                          addr_wid=48,
 268                          mask_wid=8,
 269                          reg_wid=64,
 270                          units=units)
 271     dut = TestIssuer(pspec)
 272     vl = main(dut, ports=dut.ports(), name="test_issuer")
 273
 274     if len(sys.argv) == 1:
 275         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 276         with open("test_issuer.il", "w") as f:
 277             f.write(vl)