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more openpower-isa conversion
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from openpower.decoder.power_decoder import create_pdecode
27 from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from openpower.decoder.decode2execute1 import Data
30 from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
31 SVP64PredMode)
32 from openpower.state import CoreState
33 from openpower.consts import (CR, SVP64CROffs)
34 from soc.experiment.testmem import TestMemory # test only for instructions
35 from soc.regfile.regfiles import StateRegs, FastRegs
36 from soc.simple.core import NonProductionCore
37 from soc.config.test.test_loadstore import TestMemPspec
38 from soc.config.ifetch import ConfigFetchUnit
39 from soc.debug.dmi import CoreDebug, DMIInterface
40 from soc.debug.jtag import JTAG
41 from soc.config.pinouts import get_pinspecs
42 from soc.interrupts.xics import XICS_ICP, XICS_ICS
43 from soc.bus.simple_gpio import SimpleGPIO
44 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
45 from soc.clock.select import ClockSelect
46 from soc.clock.dummypll import DummyPLL
47 from openpower.sv.svstate import SVSTATERec
48
49
50 from nmutil.util import rising_edge
51
52 def get_insn(f_instr_o, pc):
53 if f_instr_o.width == 32:
54 return f_instr_o
55 else:
56 # 64-bit: bit 2 of pc decides which word to select
57 return f_instr_o.word_select(pc[2], 32)
58
59 # gets state input or reads from state regfile
60 def state_get(m, core_rst, state_i, name, regfile, regnum):
61 comb = m.d.comb
62 sync = m.d.sync
63 # read the PC
64 res = Signal(64, reset_less=True, name=name)
65 res_ok_delay = Signal(name="%s_ok_delay" % name)
66 with m.If(~core_rst):
67 sync += res_ok_delay.eq(~state_i.ok)
68 with m.If(state_i.ok):
69 # incoming override (start from pc_i)
70 comb += res.eq(state_i.data)
71 with m.Else():
72 # otherwise read StateRegs regfile for PC...
73 comb += regfile.ren.eq(1<<regnum)
74 # ... but on a 1-clock delay
75 with m.If(res_ok_delay):
76 comb += res.eq(regfile.data_o)
77 return res
78
79 def get_predint(m, mask, name):
80 """decode SVP64 predicate integer mask field to reg number and invert
81 this is identical to the equivalent function in ISACaller except that
82 it doesn't read the INT directly, it just decodes "what needs to be done"
83 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84
85 * all1s is set to indicate that no mask is to be applied.
86 * regread indicates the GPR register number to be read
87 * invert is set to indicate that the register value is to be inverted
88 * unary indicates that the contents of the register is to be shifted 1<<r3
89 """
90 comb = m.d.comb
91 regread = Signal(5, name=name+"regread")
92 invert = Signal(name=name+"invert")
93 unary = Signal(name=name+"unary")
94 all1s = Signal(name=name+"all1s")
95 with m.Switch(mask):
96 with m.Case(SVP64PredInt.ALWAYS.value):
97 comb += all1s.eq(1) # use 0b1111 (all ones)
98 with m.Case(SVP64PredInt.R3_UNARY.value):
99 comb += regread.eq(3)
100 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
101 with m.Case(SVP64PredInt.R3.value):
102 comb += regread.eq(3)
103 with m.Case(SVP64PredInt.R3_N.value):
104 comb += regread.eq(3)
105 comb += invert.eq(1)
106 with m.Case(SVP64PredInt.R10.value):
107 comb += regread.eq(10)
108 with m.Case(SVP64PredInt.R10_N.value):
109 comb += regread.eq(10)
110 comb += invert.eq(1)
111 with m.Case(SVP64PredInt.R30.value):
112 comb += regread.eq(30)
113 with m.Case(SVP64PredInt.R30_N.value):
114 comb += regread.eq(30)
115 comb += invert.eq(1)
116 return regread, invert, unary, all1s
117
118 def get_predcr(m, mask, name):
119 """decode SVP64 predicate CR to reg number field and invert status
120 this is identical to _get_predcr in ISACaller
121 """
122 comb = m.d.comb
123 idx = Signal(2, name=name+"idx")
124 invert = Signal(name=name+"crinvert")
125 with m.Switch(mask):
126 with m.Case(SVP64PredCR.LT.value):
127 comb += idx.eq(CR.LT)
128 comb += invert.eq(0)
129 with m.Case(SVP64PredCR.GE.value):
130 comb += idx.eq(CR.LT)
131 comb += invert.eq(1)
132 with m.Case(SVP64PredCR.GT.value):
133 comb += idx.eq(CR.GT)
134 comb += invert.eq(0)
135 with m.Case(SVP64PredCR.LE.value):
136 comb += idx.eq(CR.GT)
137 comb += invert.eq(1)
138 with m.Case(SVP64PredCR.EQ.value):
139 comb += idx.eq(CR.EQ)
140 comb += invert.eq(0)
141 with m.Case(SVP64PredCR.NE.value):
142 comb += idx.eq(CR.EQ)
143 comb += invert.eq(1)
144 with m.Case(SVP64PredCR.SO.value):
145 comb += idx.eq(CR.SO)
146 comb += invert.eq(0)
147 with m.Case(SVP64PredCR.NS.value):
148 comb += idx.eq(CR.SO)
149 comb += invert.eq(1)
150 return idx, invert
151
152
153 class TestIssuerInternal(Elaboratable):
154 """TestIssuer - reads instructions from TestMemory and issues them
155
156 efficiency and speed is not the main goal here: functional correctness
157 and code clarity is. optimisations (which almost 100% interfere with
158 easy understanding) come later.
159 """
160 def __init__(self, pspec):
161
162 # test is SVP64 is to be enabled
163 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
164
165 # and if regfiles are reduced
166 self.regreduce_en = (hasattr(pspec, "regreduce") and
167 (pspec.regreduce == True))
168
169 # JTAG interface. add this right at the start because if it's
170 # added it *modifies* the pspec, by adding enable/disable signals
171 # for parts of the rest of the core
172 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
173 if self.jtag_en:
174 # XXX MUST keep this up-to-date with litex, and
175 # soc-cocotb-sim, and err.. all needs sorting out, argh
176 subset = ['uart',
177 'mtwi',
178 'eint', 'gpio', 'mspi0',
179 # 'mspi1', - disabled for now
180 # 'pwm', 'sd0', - disabled for now
181 'sdr']
182 self.jtag = JTAG(get_pinspecs(subset=subset))
183 # add signals to pspec to enable/disable icache and dcache
184 # (or data and intstruction wishbone if icache/dcache not included)
185 # https://bugs.libre-soc.org/show_bug.cgi?id=520
186 # TODO: do we actually care if these are not domain-synchronised?
187 # honestly probably not.
188 pspec.wb_icache_en = self.jtag.wb_icache_en
189 pspec.wb_dcache_en = self.jtag.wb_dcache_en
190 self.wb_sram_en = self.jtag.wb_sram_en
191 else:
192 self.wb_sram_en = Const(1)
193
194 # add 4k sram blocks?
195 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
196 pspec.sram4x4kblock == True)
197 if self.sram4x4k:
198 self.sram4k = []
199 for i in range(4):
200 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
201 features={'err'}))
202
203 # add interrupt controller?
204 self.xics = hasattr(pspec, "xics") and pspec.xics == True
205 if self.xics:
206 self.xics_icp = XICS_ICP()
207 self.xics_ics = XICS_ICS()
208 self.int_level_i = self.xics_ics.int_level_i
209
210 # add GPIO peripheral?
211 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
212 if self.gpio:
213 self.simple_gpio = SimpleGPIO()
214 self.gpio_o = self.simple_gpio.gpio_o
215
216 # main instruction core. suitable for prototyping / demo only
217 self.core = core = NonProductionCore(pspec)
218
219 # instruction decoder. goes into Trap Record
220 pdecode = create_pdecode()
221 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
222 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
223 opkls=IssuerDecode2ToOperand,
224 svp64_en=self.svp64_en,
225 regreduce_en=self.regreduce_en)
226 if self.svp64_en:
227 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
228
229 # Test Instruction memory
230 self.imem = ConfigFetchUnit(pspec).fu
231
232 # DMI interface
233 self.dbg = CoreDebug()
234
235 # instruction go/monitor
236 self.pc_o = Signal(64, reset_less=True)
237 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
238 self.svstate_i = Data(32, "svstate_i") # ditto
239 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
240 self.busy_o = Signal(reset_less=True)
241 self.memerr_o = Signal(reset_less=True)
242
243 # STATE regfile read /write ports for PC, MSR, SVSTATE
244 staterf = self.core.regs.rf['state']
245 self.state_r_pc = staterf.r_ports['cia'] # PC rd
246 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
247 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
248 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
249 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
250
251 # DMI interface access
252 intrf = self.core.regs.rf['int']
253 crrf = self.core.regs.rf['cr']
254 xerrf = self.core.regs.rf['xer']
255 self.int_r = intrf.r_ports['dmi'] # INT read
256 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
257 self.xer_r = xerrf.r_ports['full_xer'] # XER read
258
259 if self.svp64_en:
260 # for predication
261 self.int_pred = intrf.r_ports['pred'] # INT predicate read
262 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
263
264 # hack method of keeping an eye on whether branch/trap set the PC
265 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
266 self.state_nia.wen.name = 'state_nia_wen'
267
268 # pulse to synchronize the simulator at instruction end
269 self.insn_done = Signal()
270
271 if self.svp64_en:
272 # store copies of predicate masks
273 self.srcmask = Signal(64)
274 self.dstmask = Signal(64)
275
276 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
277 fetch_pc_ready_o, fetch_pc_valid_i,
278 fetch_insn_valid_o, fetch_insn_ready_i):
279 """fetch FSM
280
281 this FSM performs fetch of raw instruction data, partial-decodes
282 it 32-bit at a time to detect SVP64 prefixes, and will optionally
283 read a 2nd 32-bit quantity if that occurs.
284 """
285 comb = m.d.comb
286 sync = m.d.sync
287 pdecode2 = self.pdecode2
288 cur_state = self.cur_state
289 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
290
291 msr_read = Signal(reset=1)
292
293 with m.FSM(name='fetch_fsm'):
294
295 # waiting (zzz)
296 with m.State("IDLE"):
297 comb += fetch_pc_ready_o.eq(1)
298 with m.If(fetch_pc_valid_i):
299 # instruction allowed to go: start by reading the PC
300 # capture the PC and also drop it into Insn Memory
301 # we have joined a pair of combinatorial memory
302 # lookups together. this is Generally Bad.
303 comb += self.imem.a_pc_i.eq(pc)
304 comb += self.imem.a_valid_i.eq(1)
305 comb += self.imem.f_valid_i.eq(1)
306 sync += cur_state.pc.eq(pc)
307 sync += cur_state.svstate.eq(svstate) # and svstate
308
309 # initiate read of MSR. arrives one clock later
310 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
311 sync += msr_read.eq(0)
312
313 m.next = "INSN_READ" # move to "wait for bus" phase
314
315 # dummy pause to find out why simulation is not keeping up
316 with m.State("INSN_READ"):
317 # one cycle later, msr/sv read arrives. valid only once.
318 with m.If(~msr_read):
319 sync += msr_read.eq(1) # yeah don't read it again
320 sync += cur_state.msr.eq(self.state_r_msr.data_o)
321 with m.If(self.imem.f_busy_o): # zzz...
322 # busy: stay in wait-read
323 comb += self.imem.a_valid_i.eq(1)
324 comb += self.imem.f_valid_i.eq(1)
325 with m.Else():
326 # not busy: instruction fetched
327 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
328 if self.svp64_en:
329 svp64 = self.svp64
330 # decode the SVP64 prefix, if any
331 comb += svp64.raw_opcode_in.eq(insn)
332 comb += svp64.bigendian.eq(self.core_bigendian_i)
333 # pass the decoded prefix (if any) to PowerDecoder2
334 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
335 # remember whether this is a prefixed instruction, so
336 # the FSM can readily loop when VL==0
337 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
338 # calculate the address of the following instruction
339 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
340 sync += nia.eq(cur_state.pc + insn_size)
341 with m.If(~svp64.is_svp64_mode):
342 # with no prefix, store the instruction
343 # and hand it directly to the next FSM
344 sync += dec_opcode_i.eq(insn)
345 m.next = "INSN_READY"
346 with m.Else():
347 # fetch the rest of the instruction from memory
348 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
349 comb += self.imem.a_valid_i.eq(1)
350 comb += self.imem.f_valid_i.eq(1)
351 m.next = "INSN_READ2"
352 else:
353 # not SVP64 - 32-bit only
354 sync += nia.eq(cur_state.pc + 4)
355 sync += dec_opcode_i.eq(insn)
356 m.next = "INSN_READY"
357
358 with m.State("INSN_READ2"):
359 with m.If(self.imem.f_busy_o): # zzz...
360 # busy: stay in wait-read
361 comb += self.imem.a_valid_i.eq(1)
362 comb += self.imem.f_valid_i.eq(1)
363 with m.Else():
364 # not busy: instruction fetched
365 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
366 sync += dec_opcode_i.eq(insn)
367 m.next = "INSN_READY"
368 # TODO: probably can start looking at pdecode2.rm_dec
369 # here or maybe even in INSN_READ state, if svp64_mode
370 # detected, in order to trigger - and wait for - the
371 # predicate reading.
372 if self.svp64_en:
373 pmode = pdecode2.rm_dec.predmode
374 """
375 if pmode != SVP64PredMode.ALWAYS.value:
376 fire predicate loading FSM and wait before
377 moving to INSN_READY
378 else:
379 sync += self.srcmask.eq(-1) # set to all 1s
380 sync += self.dstmask.eq(-1) # set to all 1s
381 m.next = "INSN_READY"
382 """
383
384 with m.State("INSN_READY"):
385 # hand over the instruction, to be decoded
386 comb += fetch_insn_valid_o.eq(1)
387 with m.If(fetch_insn_ready_i):
388 m.next = "IDLE"
389
390 def fetch_predicate_fsm(self, m,
391 pred_insn_valid_i, pred_insn_ready_o,
392 pred_mask_valid_o, pred_mask_ready_i):
393 """fetch_predicate_fsm - obtains (constructs in the case of CR)
394 src/dest predicate masks
395
396 https://bugs.libre-soc.org/show_bug.cgi?id=617
397 the predicates can be read here, by using IntRegs r_ports['pred']
398 or CRRegs r_ports['pred']. in the case of CRs it will have to
399 be done through multiple reads, extracting one relevant at a time.
400 later, a faster way would be to use the 32-bit-wide CR port but
401 this is more complex decoding, here. equivalent code used in
402 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
403
404 note: this ENTIRE FSM is not to be called when svp64 is disabled
405 """
406 comb = m.d.comb
407 sync = m.d.sync
408 pdecode2 = self.pdecode2
409 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
410 predmode = rm_dec.predmode
411 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
412 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
413 # get src/dst step, so we can skip already used mask bits
414 cur_state = self.cur_state
415 srcstep = cur_state.svstate.srcstep
416 dststep = cur_state.svstate.dststep
417 cur_vl = cur_state.svstate.vl
418
419 # decode predicates
420 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
421 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
422 sidx, scrinvert = get_predcr(m, srcpred, 's')
423 didx, dcrinvert = get_predcr(m, dstpred, 'd')
424
425 with m.FSM(name="fetch_predicate"):
426
427 with m.State("FETCH_PRED_IDLE"):
428 comb += pred_insn_ready_o.eq(1)
429 with m.If(pred_insn_valid_i):
430 with m.If(predmode == SVP64PredMode.INT):
431 # skip fetching destination mask register, when zero
432 with m.If(dall1s):
433 sync += self.dstmask.eq(-1)
434 # directly go to fetch source mask register
435 # guaranteed not to be zero (otherwise predmode
436 # would be SVP64PredMode.ALWAYS, not INT)
437 comb += int_pred.addr.eq(sregread)
438 comb += int_pred.ren.eq(1)
439 m.next = "INT_SRC_READ"
440 # fetch destination predicate register
441 with m.Else():
442 comb += int_pred.addr.eq(dregread)
443 comb += int_pred.ren.eq(1)
444 m.next = "INT_DST_READ"
445 with m.Elif(predmode == SVP64PredMode.CR):
446 # go fetch masks from the CR register file
447 sync += self.srcmask.eq(0)
448 sync += self.dstmask.eq(0)
449 m.next = "CR_READ"
450 with m.Else():
451 sync += self.srcmask.eq(-1)
452 sync += self.dstmask.eq(-1)
453 m.next = "FETCH_PRED_DONE"
454
455 with m.State("INT_DST_READ"):
456 # store destination mask
457 inv = Repl(dinvert, 64)
458 new_dstmask = Signal(64)
459 with m.If(dunary):
460 # set selected mask bit for 1<<r3 mode
461 dst_shift = Signal(range(64))
462 comb += dst_shift.eq(self.int_pred.data_o & 0b111111)
463 comb += new_dstmask.eq(1 << dst_shift)
464 with m.Else():
465 # invert mask if requested
466 comb += new_dstmask.eq(self.int_pred.data_o ^ inv)
467 # shift-out already used mask bits
468 sync += self.dstmask.eq(new_dstmask >> dststep)
469 # skip fetching source mask register, when zero
470 with m.If(sall1s):
471 sync += self.srcmask.eq(-1)
472 m.next = "FETCH_PRED_DONE"
473 # fetch source predicate register
474 with m.Else():
475 comb += int_pred.addr.eq(sregread)
476 comb += int_pred.ren.eq(1)
477 m.next = "INT_SRC_READ"
478
479 with m.State("INT_SRC_READ"):
480 # store source mask
481 inv = Repl(sinvert, 64)
482 new_srcmask = Signal(64)
483 with m.If(sunary):
484 # set selected mask bit for 1<<r3 mode
485 src_shift = Signal(range(64))
486 comb += src_shift.eq(self.int_pred.data_o & 0b111111)
487 comb += new_srcmask.eq(1 << src_shift)
488 with m.Else():
489 # invert mask if requested
490 comb += new_srcmask.eq(self.int_pred.data_o ^ inv)
491 # shift-out already used mask bits
492 sync += self.srcmask.eq(new_srcmask >> srcstep)
493 m.next = "FETCH_PRED_DONE"
494
495 # fetch masks from the CR register file
496 # implements the following loop:
497 # idx, inv = get_predcr(mask)
498 # mask = 0
499 # for cr_idx in range(vl):
500 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle to complete
501 # if cr[idx] ^ inv:
502 # mask |= 1 << cr_idx
503 # return mask
504 with m.State("CR_READ"):
505 # the CR index to be read, which will be ready by the next cycle
506 cr_idx = Signal.like(cur_vl, reset_less=True)
507 # submit the read operation to the regfile
508 with m.If(cr_idx != cur_vl):
509 # the CR read port is unary ...
510 # ren = 1 << cr_idx
511 # ... in MSB0 convention ...
512 # ren = 1 << (7 - cr_idx)
513 # ... and with an offset:
514 # ren = 1 << (7 - off - cr_idx)
515 comb += cr_pred.ren.eq(1 << (7 - SVP64CROffs.CRPred - cr_idx))
516 # signal data valid in the next cycle
517 cr_read = Signal(reset_less=True)
518 sync += cr_read.eq(1)
519 # load the next index
520 sync += cr_idx.eq(cr_idx + 1)
521 with m.Else():
522 # exit on loop end
523 sync += cr_read.eq(0)
524 sync += cr_idx.eq(0)
525 m.next = "FETCH_PRED_DONE"
526 with m.If(cr_read):
527 # compensate for the one cycle delay on the regfile
528 cur_cr_idx = Signal.like(cur_vl)
529 comb += cur_cr_idx.eq(cr_idx - 1)
530 # read the CR field, select the appropriate bit
531 cr_field = Signal(4)
532 scr_bit = Signal()
533 dcr_bit = Signal()
534 comb += cr_field.eq(cr_pred.data_o)
535 comb += scr_bit.eq(cr_field.bit_select(sidx, 1) ^ scrinvert)
536 comb += dcr_bit.eq(cr_field.bit_select(didx, 1) ^ dcrinvert)
537 # set the corresponding mask bit
538 bit_to_set = Signal.like(self.srcmask)
539 comb += bit_to_set.eq(1 << cur_cr_idx)
540 with m.If(scr_bit):
541 sync += self.srcmask.eq(self.srcmask | bit_to_set)
542 with m.If(dcr_bit):
543 sync += self.dstmask.eq(self.dstmask | bit_to_set)
544
545 with m.State("FETCH_PRED_DONE"):
546 comb += pred_mask_valid_o.eq(1)
547 with m.If(pred_mask_ready_i):
548 m.next = "FETCH_PRED_IDLE"
549
550 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
551 dbg, core_rst, is_svp64_mode,
552 fetch_pc_ready_o, fetch_pc_valid_i,
553 fetch_insn_valid_o, fetch_insn_ready_i,
554 pred_insn_valid_i, pred_insn_ready_o,
555 pred_mask_valid_o, pred_mask_ready_i,
556 exec_insn_valid_i, exec_insn_ready_o,
557 exec_pc_valid_o, exec_pc_ready_i):
558 """issue FSM
559
560 decode / issue FSM. this interacts with the "fetch" FSM
561 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
562 (outgoing). also interacts with the "execute" FSM
563 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
564 (incoming).
565 SVP64 RM prefixes have already been set up by the
566 "fetch" phase, so execute is fairly straightforward.
567 """
568
569 comb = m.d.comb
570 sync = m.d.sync
571 pdecode2 = self.pdecode2
572 cur_state = self.cur_state
573
574 # temporaries
575 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
576
577 # for updating svstate (things like srcstep etc.)
578 update_svstate = Signal() # set this (below) if updating
579 new_svstate = SVSTATERec("new_svstate")
580 comb += new_svstate.eq(cur_state.svstate)
581
582 # precalculate srcstep+1 and dststep+1
583 cur_srcstep = cur_state.svstate.srcstep
584 cur_dststep = cur_state.svstate.dststep
585 next_srcstep = Signal.like(cur_srcstep)
586 next_dststep = Signal.like(cur_dststep)
587 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
588 comb += next_dststep.eq(cur_state.svstate.dststep+1)
589
590 with m.FSM(name="issue_fsm"):
591
592 # sync with the "fetch" phase which is reading the instruction
593 # at this point, there is no instruction running, that
594 # could inadvertently update the PC.
595 with m.State("ISSUE_START"):
596 # wait on "core stop" release, before next fetch
597 # need to do this here, in case we are in a VL==0 loop
598 with m.If(~dbg.core_stop_o & ~core_rst):
599 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
600 with m.If(fetch_pc_ready_o): # fetch acknowledged us
601 m.next = "INSN_WAIT"
602 with m.Else():
603 # tell core it's stopped, and acknowledge debug handshake
604 comb += dbg.core_stopped_i.eq(1)
605 # while stopped, allow updating the PC and SVSTATE
606 with m.If(self.pc_i.ok):
607 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
608 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
609 sync += pc_changed.eq(1)
610 with m.If(self.svstate_i.ok):
611 comb += new_svstate.eq(self.svstate_i.data)
612 comb += update_svstate.eq(1)
613 sync += sv_changed.eq(1)
614
615 # wait for an instruction to arrive from Fetch
616 with m.State("INSN_WAIT"):
617 comb += fetch_insn_ready_i.eq(1)
618 with m.If(fetch_insn_valid_o):
619 # loop into ISSUE_START if it's a SVP64 instruction
620 # and VL == 0. this because VL==0 is a for-loop
621 # from 0 to 0 i.e. always, always a NOP.
622 cur_vl = cur_state.svstate.vl
623 with m.If(is_svp64_mode & (cur_vl == 0)):
624 # update the PC before fetching the next instruction
625 # since we are in a VL==0 loop, no instruction was
626 # executed that we could be overwriting
627 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
628 comb += self.state_w_pc.data_i.eq(nia)
629 comb += self.insn_done.eq(1)
630 m.next = "ISSUE_START"
631 with m.Else():
632 if self.svp64_en:
633 m.next = "PRED_START" # start fetching predicate
634 else:
635 m.next = "DECODE_SV" # skip predication
636
637 with m.State("PRED_START"):
638 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
639 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
640 m.next = "MASK_WAIT"
641
642 with m.State("MASK_WAIT"):
643 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
644 with m.If(pred_mask_valid_o): # predication masks are ready
645 m.next = "PRED_SKIP"
646
647 # skip zeros in predicate
648 with m.State("PRED_SKIP"):
649 with m.If(~is_svp64_mode):
650 m.next = "DECODE_SV" # nothing to do
651 with m.Else():
652 if self.svp64_en:
653 pred_src_zero = pdecode2.rm_dec.pred_sz
654 pred_dst_zero = pdecode2.rm_dec.pred_dz
655
656 # new srcstep, after skipping zeros
657 skip_srcstep = Signal.like(cur_srcstep)
658 # value to be added to the current srcstep
659 src_delta = Signal.like(cur_srcstep)
660 # add leading zeros to srcstep, if not in zero mode
661 with m.If(~pred_src_zero):
662 # priority encoder (count leading zeros)
663 # append guard bit, in case the mask is all zeros
664 pri_enc_src = PriorityEncoder(65)
665 m.submodules.pri_enc_src = pri_enc_src
666 comb += pri_enc_src.i.eq(Cat(self.srcmask,
667 Const(1, 1)))
668 comb += src_delta.eq(pri_enc_src.o)
669 # apply delta to srcstep
670 comb += skip_srcstep.eq(cur_srcstep + src_delta)
671 # shift-out all leading zeros from the mask
672 # plus the leading "one" bit
673 # TODO count leading zeros and shift-out the zero
674 # bits, in the same step, in hardware
675 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
676
677 # same as above, but for dststep
678 skip_dststep = Signal.like(cur_dststep)
679 dst_delta = Signal.like(cur_dststep)
680 with m.If(~pred_dst_zero):
681 pri_enc_dst = PriorityEncoder(65)
682 m.submodules.pri_enc_dst = pri_enc_dst
683 comb += pri_enc_dst.i.eq(Cat(self.dstmask,
684 Const(1, 1)))
685 comb += dst_delta.eq(pri_enc_dst.o)
686 comb += skip_dststep.eq(cur_dststep + dst_delta)
687 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
688
689 # TODO: initialize mask[VL]=1 to avoid passing past VL
690 with m.If((skip_srcstep >= cur_vl) |
691 (skip_dststep >= cur_vl)):
692 # end of VL loop. Update PC and reset src/dst step
693 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
694 comb += self.state_w_pc.data_i.eq(nia)
695 comb += new_svstate.srcstep.eq(0)
696 comb += new_svstate.dststep.eq(0)
697 comb += update_svstate.eq(1)
698 # synchronize with the simulator
699 comb += self.insn_done.eq(1)
700 # go back to Issue
701 m.next = "ISSUE_START"
702 with m.Else():
703 # update new src/dst step
704 comb += new_svstate.srcstep.eq(skip_srcstep)
705 comb += new_svstate.dststep.eq(skip_dststep)
706 comb += update_svstate.eq(1)
707 # proceed to Decode
708 m.next = "DECODE_SV"
709
710 # after src/dst step have been updated, we are ready
711 # to decode the instruction
712 with m.State("DECODE_SV"):
713 # decode the instruction
714 sync += core.e.eq(pdecode2.e)
715 sync += core.state.eq(cur_state)
716 sync += core.raw_insn_i.eq(dec_opcode_i)
717 sync += core.bigendian_i.eq(self.core_bigendian_i)
718 # set RA_OR_ZERO detection in satellite decoders
719 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
720 m.next = "INSN_EXECUTE" # move to "execute"
721
722 # handshake with execution FSM, move to "wait" once acknowledged
723 with m.State("INSN_EXECUTE"):
724 comb += exec_insn_valid_i.eq(1) # trigger execute
725 with m.If(exec_insn_ready_o): # execute acknowledged us
726 m.next = "EXECUTE_WAIT"
727
728 with m.State("EXECUTE_WAIT"):
729 # wait on "core stop" release, at instruction end
730 # need to do this here, in case we are in a VL>1 loop
731 with m.If(~dbg.core_stop_o & ~core_rst):
732 comb += exec_pc_ready_i.eq(1)
733 with m.If(exec_pc_valid_o):
734
735 # was this the last loop iteration?
736 is_last = Signal()
737 cur_vl = cur_state.svstate.vl
738 comb += is_last.eq(next_srcstep == cur_vl)
739
740 # if either PC or SVSTATE were changed by the previous
741 # instruction, go directly back to Fetch, without
742 # updating either PC or SVSTATE
743 with m.If(pc_changed | sv_changed):
744 m.next = "ISSUE_START"
745
746 # also return to Fetch, when no output was a vector
747 # (regardless of SRCSTEP and VL), or when the last
748 # instruction was really the last one of the VL loop
749 with m.Elif((~pdecode2.loop_continue) | is_last):
750 # before going back to fetch, update the PC state
751 # register with the NIA.
752 # ok here we are not reading the branch unit.
753 # TODO: this just blithely overwrites whatever
754 # pipeline updated the PC
755 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
756 comb += self.state_w_pc.data_i.eq(nia)
757 # reset SRCSTEP before returning to Fetch
758 if self.svp64_en:
759 with m.If(pdecode2.loop_continue):
760 comb += new_svstate.srcstep.eq(0)
761 comb += new_svstate.dststep.eq(0)
762 comb += update_svstate.eq(1)
763 else:
764 comb += new_svstate.srcstep.eq(0)
765 comb += new_svstate.dststep.eq(0)
766 comb += update_svstate.eq(1)
767 m.next = "ISSUE_START"
768
769 # returning to Execute? then, first update SRCSTEP
770 with m.Else():
771 comb += new_svstate.srcstep.eq(next_srcstep)
772 comb += new_svstate.dststep.eq(next_dststep)
773 comb += update_svstate.eq(1)
774 # return to mask skip loop
775 m.next = "PRED_SKIP"
776
777 with m.Else():
778 comb += dbg.core_stopped_i.eq(1)
779 # while stopped, allow updating the PC and SVSTATE
780 with m.If(self.pc_i.ok):
781 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
782 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
783 sync += pc_changed.eq(1)
784 with m.If(self.svstate_i.ok):
785 comb += new_svstate.eq(self.svstate_i.data)
786 comb += update_svstate.eq(1)
787 sync += sv_changed.eq(1)
788
789 # check if svstate needs updating: if so, write it to State Regfile
790 with m.If(update_svstate):
791 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
792 comb += self.state_w_sv.data_i.eq(new_svstate)
793 sync += cur_state.svstate.eq(new_svstate) # for next clock
794
795 def execute_fsm(self, m, core, pc_changed, sv_changed,
796 exec_insn_valid_i, exec_insn_ready_o,
797 exec_pc_valid_o, exec_pc_ready_i):
798 """execute FSM
799
800 execute FSM. this interacts with the "issue" FSM
801 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
802 (outgoing). SVP64 RM prefixes have already been set up by the
803 "issue" phase, so execute is fairly straightforward.
804 """
805
806 comb = m.d.comb
807 sync = m.d.sync
808 pdecode2 = self.pdecode2
809
810 # temporaries
811 core_busy_o = core.busy_o # core is busy
812 core_ivalid_i = core.ivalid_i # instruction is valid
813 core_issue_i = core.issue_i # instruction is issued
814 insn_type = core.e.do.insn_type # instruction MicroOp type
815
816 with m.FSM(name="exec_fsm"):
817
818 # waiting for instruction bus (stays there until not busy)
819 with m.State("INSN_START"):
820 comb += exec_insn_ready_o.eq(1)
821 with m.If(exec_insn_valid_i):
822 comb += core_ivalid_i.eq(1) # instruction is valid
823 comb += core_issue_i.eq(1) # and issued
824 sync += sv_changed.eq(0)
825 sync += pc_changed.eq(0)
826 m.next = "INSN_ACTIVE" # move to "wait completion"
827
828 # instruction started: must wait till it finishes
829 with m.State("INSN_ACTIVE"):
830 with m.If(insn_type != MicrOp.OP_NOP):
831 comb += core_ivalid_i.eq(1) # instruction is valid
832 # note changes to PC and SVSTATE
833 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
834 sync += sv_changed.eq(1)
835 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
836 sync += pc_changed.eq(1)
837 with m.If(~core_busy_o): # instruction done!
838 comb += exec_pc_valid_o.eq(1)
839 with m.If(exec_pc_ready_i):
840 comb += self.insn_done.eq(1)
841 m.next = "INSN_START" # back to fetch
842
843 def setup_peripherals(self, m):
844 comb, sync = m.d.comb, m.d.sync
845
846 m.submodules.core = core = DomainRenamer("coresync")(self.core)
847 m.submodules.imem = imem = self.imem
848 m.submodules.dbg = dbg = self.dbg
849 if self.jtag_en:
850 m.submodules.jtag = jtag = self.jtag
851 # TODO: UART2GDB mux, here, from external pin
852 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
853 sync += dbg.dmi.connect_to(jtag.dmi)
854
855 cur_state = self.cur_state
856
857 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
858 if self.sram4x4k:
859 for i, sram in enumerate(self.sram4k):
860 m.submodules["sram4k_%d" % i] = sram
861 comb += sram.enable.eq(self.wb_sram_en)
862
863 # XICS interrupt handler
864 if self.xics:
865 m.submodules.xics_icp = icp = self.xics_icp
866 m.submodules.xics_ics = ics = self.xics_ics
867 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
868 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
869
870 # GPIO test peripheral
871 if self.gpio:
872 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
873
874 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
875 # XXX causes litex ECP5 test to get wrong idea about input and output
876 # (but works with verilator sim *sigh*)
877 #if self.gpio and self.xics:
878 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
879
880 # instruction decoder
881 pdecode = create_pdecode()
882 m.submodules.dec2 = pdecode2 = self.pdecode2
883 if self.svp64_en:
884 m.submodules.svp64 = svp64 = self.svp64
885
886 # convenience
887 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
888 intrf = self.core.regs.rf['int']
889
890 # clock delay power-on reset
891 cd_por = ClockDomain(reset_less=True)
892 cd_sync = ClockDomain()
893 core_sync = ClockDomain("coresync")
894 m.domains += cd_por, cd_sync, core_sync
895
896 ti_rst = Signal(reset_less=True)
897 delay = Signal(range(4), reset=3)
898 with m.If(delay != 0):
899 m.d.por += delay.eq(delay - 1)
900 comb += cd_por.clk.eq(ClockSignal())
901
902 # power-on reset delay
903 core_rst = ResetSignal("coresync")
904 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
905 comb += core_rst.eq(ti_rst)
906
907 # busy/halted signals from core
908 comb += self.busy_o.eq(core.busy_o)
909 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
910
911 # temporary hack: says "go" immediately for both address gen and ST
912 l0 = core.l0
913 ldst = core.fus.fus['ldst0']
914 st_go_edge = rising_edge(m, ldst.st.rel_o)
915 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
916 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
917
918 return core_rst
919
920 def elaborate(self, platform):
921 m = Module()
922 # convenience
923 comb, sync = m.d.comb, m.d.sync
924 cur_state = self.cur_state
925 pdecode2 = self.pdecode2
926 dbg = self.dbg
927 core = self.core
928
929 # set up peripherals and core
930 core_rst = self.setup_peripherals(m)
931
932 # reset current state if core reset requested
933 with m.If(core_rst):
934 m.d.sync += self.cur_state.eq(0)
935
936 # PC and instruction from I-Memory
937 comb += self.pc_o.eq(cur_state.pc)
938 pc_changed = Signal() # note write to PC
939 sv_changed = Signal() # note write to SVSTATE
940
941 # read state either from incoming override or from regfile
942 # TODO: really should be doing MSR in the same way
943 pc = state_get(m, core_rst, self.pc_i,
944 "pc", # read PC
945 self.state_r_pc, StateRegs.PC)
946 svstate = state_get(m, core_rst, self.svstate_i,
947 "svstate", # read SVSTATE
948 self.state_r_sv, StateRegs.SVSTATE)
949
950 # don't write pc every cycle
951 comb += self.state_w_pc.wen.eq(0)
952 comb += self.state_w_pc.data_i.eq(0)
953
954 # don't read msr every cycle
955 comb += self.state_r_msr.ren.eq(0)
956
957 # address of the next instruction, in the absence of a branch
958 # depends on the instruction size
959 nia = Signal(64)
960
961 # connect up debug signals
962 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
963 comb += dbg.terminate_i.eq(core.core_terminate_o)
964 comb += dbg.state.pc.eq(pc)
965 comb += dbg.state.svstate.eq(svstate)
966 comb += dbg.state.msr.eq(cur_state.msr)
967
968 # pass the prefix mode from Fetch to Issue, so the latter can loop
969 # on VL==0
970 is_svp64_mode = Signal()
971
972 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
973 # these are the handshake signals between fetch and decode/execute
974
975 # fetch FSM can run as soon as the PC is valid
976 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
977 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
978
979 # fetch FSM hands over the instruction to be decoded / issued
980 fetch_insn_valid_o = Signal()
981 fetch_insn_ready_i = Signal()
982
983 # predicate fetch FSM decodes and fetches the predicate
984 pred_insn_valid_i = Signal()
985 pred_insn_ready_o = Signal()
986
987 # predicate fetch FSM delivers the masks
988 pred_mask_valid_o = Signal()
989 pred_mask_ready_i = Signal()
990
991 # issue FSM delivers the instruction to the be executed
992 exec_insn_valid_i = Signal()
993 exec_insn_ready_o = Signal()
994
995 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
996 exec_pc_valid_o = Signal()
997 exec_pc_ready_i = Signal()
998
999 # the FSMs here are perhaps unusual in that they detect conditions
1000 # then "hold" information, combinatorially, for the core
1001 # (as opposed to using sync - which would be on a clock's delay)
1002 # this includes the actual opcode, valid flags and so on.
1003
1004 # Fetch, then predicate fetch, then Issue, then Execute.
1005 # Issue is where the VL for-loop # lives. the ready/valid
1006 # signalling is used to communicate between the four.
1007
1008 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
1009 fetch_pc_ready_o, fetch_pc_valid_i,
1010 fetch_insn_valid_o, fetch_insn_ready_i)
1011
1012 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
1013 dbg, core_rst, is_svp64_mode,
1014 fetch_pc_ready_o, fetch_pc_valid_i,
1015 fetch_insn_valid_o, fetch_insn_ready_i,
1016 pred_insn_valid_i, pred_insn_ready_o,
1017 pred_mask_valid_o, pred_mask_ready_i,
1018 exec_insn_valid_i, exec_insn_ready_o,
1019 exec_pc_valid_o, exec_pc_ready_i)
1020
1021 if self.svp64_en:
1022 self.fetch_predicate_fsm(m,
1023 pred_insn_valid_i, pred_insn_ready_o,
1024 pred_mask_valid_o, pred_mask_ready_i)
1025
1026 self.execute_fsm(m, core, pc_changed, sv_changed,
1027 exec_insn_valid_i, exec_insn_ready_o,
1028 exec_pc_valid_o, exec_pc_ready_i)
1029
1030 # whatever was done above, over-ride it if core reset is held
1031 with m.If(core_rst):
1032 sync += nia.eq(0)
1033
1034 # this bit doesn't have to be in the FSM: connect up to read
1035 # regfiles on demand from DMI
1036 self.do_dmi(m, dbg)
1037
1038 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
1039 # (which uses that in PowerDecoder2 to raise 0x900 exception)
1040 self.tb_dec_fsm(m, cur_state.dec)
1041
1042 return m
1043
1044 def do_dmi(self, m, dbg):
1045 """deals with DMI debug requests
1046
1047 currently only provides read requests for the INT regfile, CR and XER
1048 it will later also deal with *writing* to these regfiles.
1049 """
1050 comb = m.d.comb
1051 sync = m.d.sync
1052 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
1053 intrf = self.core.regs.rf['int']
1054
1055 with m.If(d_reg.req): # request for regfile access being made
1056 # TODO: error-check this
1057 # XXX should this be combinatorial? sync better?
1058 if intrf.unary:
1059 comb += self.int_r.ren.eq(1<<d_reg.addr)
1060 else:
1061 comb += self.int_r.addr.eq(d_reg.addr)
1062 comb += self.int_r.ren.eq(1)
1063 d_reg_delay = Signal()
1064 sync += d_reg_delay.eq(d_reg.req)
1065 with m.If(d_reg_delay):
1066 # data arrives one clock later
1067 comb += d_reg.data.eq(self.int_r.data_o)
1068 comb += d_reg.ack.eq(1)
1069
1070 # sigh same thing for CR debug
1071 with m.If(d_cr.req): # request for regfile access being made
1072 comb += self.cr_r.ren.eq(0b11111111) # enable all
1073 d_cr_delay = Signal()
1074 sync += d_cr_delay.eq(d_cr.req)
1075 with m.If(d_cr_delay):
1076 # data arrives one clock later
1077 comb += d_cr.data.eq(self.cr_r.data_o)
1078 comb += d_cr.ack.eq(1)
1079
1080 # aaand XER...
1081 with m.If(d_xer.req): # request for regfile access being made
1082 comb += self.xer_r.ren.eq(0b111111) # enable all
1083 d_xer_delay = Signal()
1084 sync += d_xer_delay.eq(d_xer.req)
1085 with m.If(d_xer_delay):
1086 # data arrives one clock later
1087 comb += d_xer.data.eq(self.xer_r.data_o)
1088 comb += d_xer.ack.eq(1)
1089
1090 def tb_dec_fsm(self, m, spr_dec):
1091 """tb_dec_fsm
1092
1093 this is a FSM for updating either dec or tb. it runs alternately
1094 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1095 value to DEC, however the regfile has "passthrough" on it so this
1096 *should* be ok.
1097
1098 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1099 """
1100
1101 comb, sync = m.d.comb, m.d.sync
1102 fast_rf = self.core.regs.rf['fast']
1103 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1104 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1105
1106 with m.FSM() as fsm:
1107
1108 # initiates read of current DEC
1109 with m.State("DEC_READ"):
1110 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1111 comb += fast_r_dectb.ren.eq(1)
1112 m.next = "DEC_WRITE"
1113
1114 # waits for DEC read to arrive (1 cycle), updates with new value
1115 with m.State("DEC_WRITE"):
1116 new_dec = Signal(64)
1117 # TODO: MSR.LPCR 32-bit decrement mode
1118 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1119 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1120 comb += fast_w_dectb.wen.eq(1)
1121 comb += fast_w_dectb.data_i.eq(new_dec)
1122 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1123 m.next = "TB_READ"
1124
1125 # initiates read of current TB
1126 with m.State("TB_READ"):
1127 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1128 comb += fast_r_dectb.ren.eq(1)
1129 m.next = "TB_WRITE"
1130
1131 # waits for read TB to arrive, initiates write of current TB
1132 with m.State("TB_WRITE"):
1133 new_tb = Signal(64)
1134 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1135 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1136 comb += fast_w_dectb.wen.eq(1)
1137 comb += fast_w_dectb.data_i.eq(new_tb)
1138 m.next = "DEC_READ"
1139
1140 return m
1141
1142 def __iter__(self):
1143 yield from self.pc_i.ports()
1144 yield self.pc_o
1145 yield self.memerr_o
1146 yield from self.core.ports()
1147 yield from self.imem.ports()
1148 yield self.core_bigendian_i
1149 yield self.busy_o
1150
1151 def ports(self):
1152 return list(self)
1153
1154 def external_ports(self):
1155 ports = self.pc_i.ports()
1156 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1157 ]
1158
1159 if self.jtag_en:
1160 ports += list(self.jtag.external_ports())
1161 else:
1162 # don't add DMI if JTAG is enabled
1163 ports += list(self.dbg.dmi.ports())
1164
1165 ports += list(self.imem.ibus.fields.values())
1166 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1167
1168 if self.sram4x4k:
1169 for sram in self.sram4k:
1170 ports += list(sram.bus.fields.values())
1171
1172 if self.xics:
1173 ports += list(self.xics_icp.bus.fields.values())
1174 ports += list(self.xics_ics.bus.fields.values())
1175 ports.append(self.int_level_i)
1176
1177 if self.gpio:
1178 ports += list(self.simple_gpio.bus.fields.values())
1179 ports.append(self.gpio_o)
1180
1181 return ports
1182
1183 def ports(self):
1184 return list(self)
1185
1186
1187 class TestIssuer(Elaboratable):
1188 def __init__(self, pspec):
1189 self.ti = TestIssuerInternal(pspec)
1190
1191 self.pll = DummyPLL()
1192
1193 # PLL direct clock or not
1194 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1195 if self.pll_en:
1196 self.pll_18_o = Signal(reset_less=True)
1197 self.clk_sel_i = Signal(reset_less=True)
1198
1199 def elaborate(self, platform):
1200 m = Module()
1201 comb = m.d.comb
1202
1203 # TestIssuer runs at direct clock
1204 m.submodules.ti = ti = self.ti
1205 cd_int = ClockDomain("coresync")
1206
1207 if self.pll_en:
1208 # ClockSelect runs at PLL output internal clock rate
1209 m.submodules.pll = pll = self.pll
1210
1211 # add clock domains from PLL
1212 cd_pll = ClockDomain("pllclk")
1213 m.domains += cd_pll
1214
1215 # PLL clock established. has the side-effect of running clklsel
1216 # at the PLL's speed (see DomainRenamer("pllclk") above)
1217 pllclk = ClockSignal("pllclk")
1218 comb += pllclk.eq(pll.clk_pll_o)
1219
1220 # wire up external 24mhz to PLL
1221 comb += pll.clk_24_i.eq(ClockSignal())
1222
1223 # output 18 mhz PLL test signal
1224 comb += self.pll_18_o.eq(pll.pll_18_o)
1225
1226 # input to pll clock selection
1227 comb += Cat(pll.sel_a0_i, pll.sel_a1_i).eq(self.clk_sel_i)
1228
1229 # now wire up ResetSignals. don't mind them being in this domain
1230 pll_rst = ResetSignal("pllclk")
1231 comb += pll_rst.eq(ResetSignal())
1232
1233 # internal clock is set to selector clock-out. has the side-effect of
1234 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1235 intclk = ClockSignal("coresync")
1236 if self.pll_en:
1237 comb += intclk.eq(pll.clk_pll_o)
1238 else:
1239 comb += intclk.eq(ClockSignal())
1240
1241 return m
1242
1243 def ports(self):
1244 return list(self.ti.ports()) + list(self.pll.ports()) + \
1245 [ClockSignal(), ResetSignal()]
1246
1247 def external_ports(self):
1248 ports = self.ti.external_ports()
1249 ports.append(ClockSignal())
1250 ports.append(ResetSignal())
1251 if self.pll_en:
1252 ports.append(self.clk_sel_i)
1253 ports.append(self.pll_18_o)
1254 ports.append(self.pll.pll_ana_o)
1255 return ports
1256
1257
1258 if __name__ == '__main__':
1259 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1260 'spr': 1,
1261 'div': 1,
1262 'mul': 1,
1263 'shiftrot': 1
1264 }
1265 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1266 imem_ifacetype='bare_wb',
1267 addr_wid=48,
1268 mask_wid=8,
1269 reg_wid=64,
1270 units=units)
1271 dut = TestIssuer(pspec)
1272 vl = main(dut, ports=dut.ports(), name="test_issuer")
1273
1274 if len(sys.argv) == 1:
1275 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1276 with open("test_issuer.il", "w") as f:
1277 f.write(vl)