src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import sys
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     units = {'alu': 1,
  13              'cr': 1, 'branch': 1, 'trap': 1,
  14             'logical': 1,
  15              'spr': 1,
  16              'div': 1,
  17              'mul': 1,
  18              'shiftrot': 1
  19                 }
  20     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  21                          imem_ifacetype='bare_wb',
  22                          addr_wid=48,
  23                          mask_wid=8,
  24                          # must leave at 64
  25                          reg_wid=64,
  26                          # set to 32 for instruction-memory width=32
  27                          imem_reg_wid=64,
  28                          # set to 32 to make data wishbone bus 32-bit
  29                          #wb_data_wid=32,
  30                          xics=True,
  31                          #nocore=True, # to help test coriolis2 ioring
  32                          gpio=True, # for test purposes
  33                          debug="jtag", # set to jtag or dmi
  34                          units=units)
  35
  36     dut = TestIssuer(pspec)
  37
  38     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  39     with open(sys.argv[1], "w") as f:
  40         f.write(vl)