1 """simple core issuer verilog generator
5 from nmigen
.cli
import verilog
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.simple
.issuer
import TestIssuer
11 if __name__
== '__main__':
13 'cr': 1, 'branch': 1, 'trap': 1,
20 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
21 imem_ifacetype
='bare_wb',
26 # set to 32 for instruction-memory width=32
28 # set to 32 to make data wishbone bus 32-bit
31 dut
= TestIssuer(pspec
)
33 vl
= verilog
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
34 with
open(sys
.argv
[1], "w") as f
: