src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--disable-xics", action="store_true",
  16                         help="Disable interrupts")
  17     parser.add_argument("--use-pll", action="store_true", help="Enable pll")
  18     parser.add_argument("--disable-gpio", action="store_true",
  19                         help="Disable gpio pins")
  20     parser.add_argument("--debug", default="jtag", help="Select debug " \
  21                         "interface [jtag | dmi] [default jtag]")
  22
  23     args = parser.parse_args()
  24
  25     print(args)
  26
  27     units = {'alu': 1,
  28              'cr': 1, 'branch': 1, 'trap': 1,
  29              'logical': 1,
  30              'spr': 1,
  31              'div': 1,
  32              'mul': 1,
  33              'shiftrot': 1
  34             }
  35     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  36                          imem_ifacetype='bare_wb',
  37                          addr_wid=48,
  38                          mask_wid=8,
  39                          # must leave at 64
  40                          reg_wid=64,
  41                          # set to 32 for instruction-memory width=32
  42                          imem_reg_wid=64,
  43                          # set to 32 to make data wishbone bus 32-bit
  44                          #wb_data_wid=32,
  45                          xics=False if args.disable_xics else True,
  46                          # to help test coriolis2 ioring
  47                          #nocore=True,
  48                          # bypass PLL
  49                          use_pll=True if args.use_pll else False,
  50                          # for test purposes
  51                          gpio=False if args.disable_gpio else True,
  52                          # set to jtag or dmi
  53                          debug=args.debug,
  54                          units=units)
  55
  56     dut = TestIssuer(pspec)
  57
  58     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  59     with open(args.output_filename, "w") as f:
  60         f.write(vl)