src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  16                         help="Enable interrupts",
  17                         default=True)
  18     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  19                         help="Disable interrupts",
  20                         default=False)
  21     parser.add_argument("--enable-core", dest='core', action="store_true",
  22                         help="Enable main core",
  23                         default=True)
  24     parser.add_argument("--disable-core", dest='core', action="store_false",
  25                         help="disable main core",
  26                         default=False)
  27     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  28                         help="Enable pll",
  29                         default=False)
  30     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  31                         help="Disable pll",
  32                         default=False)
  33     parser.add_argument("--enable-testgpio", action="store_true",
  34                         help="Disable gpio pins",
  35                         default=False)
  36     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  37                         help="Disable sram 4x4k block",
  38                         default=False)
  39     parser.add_argument("--debug", default="jtag", help="Select debug " \
  40                         "interface [jtag | dmi] [default jtag]")
  41     parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
  42                         help="Enable SVP64",
  43                         default=True)
  44     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
  45                         help="disable SVP64",
  46                         default=False)
  47
  48     args = parser.parse_args()
  49
  50     print(args)
  51
  52     units = {'alu': 1,
  53              'cr': 1, 'branch': 1, 'trap': 1,
  54              'logical': 1,
  55              'spr': 1,
  56              'div': 1,
  57              'mul': 1,
  58              'shiftrot': 1
  59             }
  60
  61     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  62                          imem_ifacetype='bare_wb',
  63                          addr_wid=48,
  64                          mask_wid=8,
  65                          # must leave at 64
  66                          reg_wid=64,
  67                          # set to 32 for instruction-memory width=32
  68                          imem_reg_wid=64,
  69                          # set to 32 to make data wishbone bus 32-bit
  70                          #wb_data_wid=32,
  71                          xics=args.xics, # XICS interrupt controller
  72                          nocore=not args.core, # test coriolis2 ioring
  73                          use_pll=args.pll,  # bypass PLL
  74                          gpio=args.enable_testgpio, # for test purposes
  75                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
  76                          debug=args.debug,      # set to jtag or dmi
  77                          svp64=args.svp64,      # enable SVP64
  78                          units=units)
  79
  80     print("nocore", pspec.__dict__["nocore"])
  81     print("gpio", pspec.__dict__["gpio"])
  82     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
  83     print("xics", pspec.__dict__["xics"])
  84     print("use_pll", pspec.__dict__["use_pll"])
  85     print("debug", pspec.__dict__["debug"])
  86     print("SVP64", pspec.__dict__["svp64"])
  87
  88     dut = TestIssuer(pspec)
  89
  90     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  91     with open(args.output_filename, "w") as f:
  92         f.write(vl)