1 """simple core issuer verilog generator
5 from nmigen
.cli
import verilog
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.simple
.issuer
import TestIssuer
11 if __name__
== '__main__':
12 parser
= argparse
.ArgumentParser(description
="Simple core issuer " \
14 parser
.add_argument("output_filename")
15 parser
.add_argument("--enable-xics", dest
='xics', action
="store_true",
16 help="Enable interrupts",
18 parser
.add_argument("--disable-xics", dest
='xics', action
="store_false",
19 help="Disable interrupts",
21 parser
.add_argument("--enable-core", dest
='core', action
="store_true",
22 help="Enable main core",
24 parser
.add_argument("--disable-core", dest
='core', action
="store_false",
25 help="disable main core",
27 parser
.add_argument("--enable-pll", dest
='pll', action
="store_true",
30 parser
.add_argument("--disable-pll", dest
='pll', action
="store_false",
33 parser
.add_argument("--enable-testgpio", action
="store_true",
34 help="Disable gpio pins",
36 parser
.add_argument("--enable-sram4x4kblock", action
="store_true",
37 help="Disable sram 4x4k block",
39 parser
.add_argument("--debug", default
="jtag", help="Select debug " \
40 "interface [jtag | dmi] [default jtag]")
42 args
= parser
.parse_args()
47 'cr': 1, 'branch': 1, 'trap': 1,
55 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
56 imem_ifacetype
='bare_wb',
61 # set to 32 for instruction-memory width=32
63 # set to 32 to make data wishbone bus 32-bit
65 xics
=args
.xics
, # XICS interrupt controller
66 nocore
=not args
.core
, # test coriolis2 ioring
67 use_pll
=args
.pll
, # bypass PLL
68 gpio
=args
.enable_testgpio
, # for test purposes
69 sram4x4kblock
=args
.enable_sram4x4kblock
, # add SRAMs
70 debug
=args
.debug
, # set to jtag or dmi
73 print("nocore", pspec
.__dict
__["nocore"])
74 print("gpio", pspec
.__dict
__["gpio"])
75 print("sram4x4kblock", pspec
.__dict
__["sram4x4kblock"])
76 print("xics", pspec
.__dict
__["xics"])
77 print("use_pll", pspec
.__dict
__["use_pll"])
78 print("debug", pspec
.__dict
__["debug"])
80 dut
= TestIssuer(pspec
)
82 vl
= verilog
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
83 with
open(args
.output_filename
, "w") as f
: