src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import sys
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
  13              'spr': 1,
  14              'mul': 1,
  15              'shiftrot': 1}
  16     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  17                          imem_ifacetype='bare_wb',
  18                          addr_wid=48,
  19                          mask_wid=8,
  20                          # must leave at 64
  21                          reg_wid=64,
  22                          # set to 32 for instruction-memory width=32
  23                          imem_reg_wid=64,
  24                          units=units)
  25     dut = TestIssuer(pspec)
  26
  27     vl = verilog.convert(dut, ports=dut.ports(), name="test_issuer")
  28     with open(sys.argv[1], "w") as f:
  29         f.write(vl)