5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.power_decoder
import create_pdecode
14 from soc
.decoder
.power_decoder2
import PowerDecode2
15 from soc
.decoder
.selectable_int
import SelectableInt
16 from soc
.decoder
.isa
.all
import ISA
17 from soc
.decoder
.power_enums
import SPR
, spr_dict
, Function
, XER_bits
18 from soc
.config
.test
.test_loadstore
import TestMemPspec
19 from soc
.config
.endian
import bigendian
21 from soc
.simple
.core
import NonProductionCore
22 from soc
.experiment
.compalu_multi
import find_ok
# hack
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
27 # test with ALU data and Logical data
28 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
29 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
30 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
31 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
32 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
33 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
34 from soc
.regfile
.util
import spr_to_fast_reg
37 def setup_regs(core
, test
):
39 # set up INT regfile, "direct" write (bypass rd/write ports)
40 intregs
= core
.regs
.int
42 yield intregs
.regs
[i
].reg
.eq(test
.regs
[i
])
44 # set up CR regfile, "direct" write across all CRs
47 #cr = int('{:32b}'.format(cr)[::-1], 2)
48 print("cr reg", hex(cr
))
51 cri
= (cr
>> (i
*4)) & 0xf
52 #cri = int('{:04b}'.format(cri)[::-1], 2)
53 print("cr reg", hex(cri
), i
,
54 crregs
.regs
[i
].reg
.shape())
55 yield crregs
.regs
[i
].reg
.eq(cri
)
57 # set up XER. "direct" write (bypass rd/write ports)
59 print("sprs", test
.sprs
)
61 if 'XER' in test
.sprs
:
62 xer
= test
.sprs
['XER']
66 if isinstance(xer
, int):
67 xer
= SelectableInt(xer
, 64)
68 sobit
= xer
[XER_bits
['SO']].value
69 yield xregs
.regs
[xregs
.SO
].reg
.eq(sobit
)
70 cabit
= xer
[XER_bits
['CA']].value
71 ca32bit
= xer
[XER_bits
['CA32']].value
72 yield xregs
.regs
[xregs
.CA
].reg
.eq(Cat(cabit
, ca32bit
))
73 ovbit
= xer
[XER_bits
['OV']].value
74 ov32bit
= xer
[XER_bits
['OV32']].value
75 yield xregs
.regs
[xregs
.OV
].reg
.eq(Cat(ovbit
, ov32bit
))
76 print("setting XER so %d ca %d ca32 %d ov %d ov32 %d" %
77 (sobit
, cabit
, ca32bit
, ovbit
, ov32bit
))
79 yield xregs
.regs
[xregs
.SO
].reg
.eq(0)
80 yield xregs
.regs
[xregs
.OV
].reg
.eq(0)
81 yield xregs
.regs
[xregs
.CA
].reg
.eq(0)
83 # setting both fast and slow SPRs from test data
85 fregs
= core
.regs
.fast
87 for sprname
, val
in test
.sprs
.items():
88 if isinstance(val
, SelectableInt
):
90 if isinstance(sprname
, int):
91 sprname
= spr_dict
[sprname
].SPR
94 fast
= spr_to_fast_reg(sprname
)
96 # match behaviour of SPRMap in power_decoder2.py
97 for i
, x
in enumerate(SPR
):
99 yield sregs
[i
].reg
.eq(val
)
100 print("setting slow SPR %d (%s) to %x" %
103 yield fregs
.regs
[fast
].reg
.eq(val
)
104 print("setting fast reg %d (%s) to %x" %
105 (fast
, sprname
, val
))
107 # allow changes to settle before reporting on XER
111 pdecode2
= core
.pdecode2
112 so
= yield xregs
.regs
[xregs
.SO
].reg
113 ov
= yield xregs
.regs
[xregs
.OV
].reg
114 ca
= yield xregs
.regs
[xregs
.CA
].reg
115 oe
= yield pdecode2
.e
.do
.oe
.oe
116 oe_ok
= yield pdecode2
.e
.do
.oe
.oe_ok
118 print("before: so/ov-32/ca-32", so
, bin(ov
), bin(ca
))
119 print("oe:", oe
, oe_ok
)
122 def check_regs(dut
, sim
, core
, test
, code
):
126 rval
= yield core
.regs
.int.regs
[i
].reg
128 print("int regs", list(map(hex, intregs
)))
130 simregval
= sim
.gpr
[i
].asint()
131 dut
.assertEqual(simregval
, intregs
[i
],
132 "int reg %d not equal %s" % (i
, repr(code
)))
137 rval
= yield core
.regs
.cr
.regs
[i
].reg
139 print("cr regs", list(map(hex, crregs
)))
142 cri
= sim
.crl
[7-i
].get_range().value
143 print("cr reg", i
, hex(cri
), i
, hex(rval
))
144 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
145 dut
.assertEqual(cri
, rval
,
146 "cr reg %d not equal %s" % (i
, repr(code
)))
149 xregs
= core
.regs
.xer
150 so
= yield xregs
.regs
[xregs
.SO
].reg
151 ov
= yield xregs
.regs
[xregs
.OV
].reg
152 ca
= yield xregs
.regs
[xregs
.CA
].reg
154 print("sim SO", sim
.spr
['XER'][XER_bits
['SO']])
155 e_so
= sim
.spr
['XER'][XER_bits
['SO']].value
156 e_ov
= sim
.spr
['XER'][XER_bits
['OV']].value
157 e_ov32
= sim
.spr
['XER'][XER_bits
['OV32']].value
158 e_ca
= sim
.spr
['XER'][XER_bits
['CA']].value
159 e_ca32
= sim
.spr
['XER'][XER_bits
['CA32']].value
161 e_ov
= e_ov |
(e_ov32
<< 1)
162 e_ca
= e_ca |
(e_ca32
<< 1)
164 print("after: so/ov-32/ca-32", so
, bin(ov
), bin(ca
))
165 dut
.assertEqual(e_so
, so
, "so mismatch %s" % (repr(code
)))
166 dut
.assertEqual(e_ov
, ov
, "ov mismatch %s" % (repr(code
)))
167 dut
.assertEqual(e_ca
, ca
, "ca mismatch %s" % (repr(code
)))
170 def wait_for_busy_hi(cu
):
172 busy_o
= yield cu
.busy_o
173 terminated_o
= yield cu
.core_terminated_o
174 if busy_o
or terminated_o
:
175 print("busy/terminated:", busy_o
, terminated_o
)
177 print("!busy", busy_o
, terminated_o
)
181 def set_issue(core
, dec2
, sim
):
182 yield core
.issue_i
.eq(1)
184 yield core
.issue_i
.eq(0)
185 yield from wait_for_busy_hi(core
)
188 def wait_for_busy_clear(cu
):
190 busy_o
= yield cu
.busy_o
191 terminated_o
= yield cu
.core_terminated_o
192 if not busy_o
or terminated_o
:
193 print("busy/terminated:", busy_o
, terminated_o
)
199 class TestRunner(FHDLTestCase
):
200 def __init__(self
, tst_data
):
201 super().__init
__("run_all")
202 self
.test_data
= tst_data
207 instruction
= Signal(32)
210 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
216 m
.submodules
.core
= core
= NonProductionCore(pspec
)
217 pdecode2
= core
.pdecode2
220 comb
+= core
.raw_opcode_i
.eq(instruction
)
221 comb
+= core
.ivalid_i
.eq(ivalid_i
)
223 # temporary hack: says "go" immediately for both address gen and ST
224 ldst
= core
.fus
.fus
['ldst0']
225 m
.d
.comb
+= ldst
.ad
.go
.eq(ldst
.ad
.rel
) # link addr-go direct to rel
226 m
.d
.comb
+= ldst
.st
.go
.eq(ldst
.st
.rel
) # link store-go direct to rel
233 yield core
.issue_i
.eq(0)
236 for test
in self
.test_data
:
238 program
= test
.program
239 self
.subTest(test
.name
)
240 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
243 gen
= program
.generate_instructions()
244 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
246 yield from setup_test_memory(l0
, sim
)
247 yield from setup_regs(core
, test
)
249 index
= sim
.pc
.CIA
.value
//4
250 while index
< len(instructions
):
251 ins
, code
= instructions
[index
]
253 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
256 # ask the decoder to decode this binary data (endian'd)
257 yield core
.bigendian_i
.eq(bigendian
) # little / big?
258 yield instruction
.eq(ins
) # raw binary instr.
261 # fn_unit = yield pdecode2.e.fn_unit
262 #fuval = self.funit.value
263 #self.assertEqual(fn_unit & fuval, fuval)
265 # set operand and get inputs
266 yield from set_issue(core
, pdecode2
, sim
)
269 yield from wait_for_busy_clear(core
)
274 # call simulated operation
275 opname
= code
.split(' ')[0]
276 yield from sim
.call(opname
)
277 index
= sim
.pc
.CIA
.value
//4
280 yield from check_regs(self
, sim
, core
, test
, code
)
283 yield from check_sim_memory(self
, l0
, sim
, code
)
285 sim
.add_sync_process(process
)
286 with sim
.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
291 if __name__
== "__main__":
292 unittest
.main(exit
=False)
293 suite
= unittest
.TestSuite()
294 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
295 suite
.addTest(TestRunner(CRTestCase
.test_data
))
296 suite
.addTest(TestRunner(ShiftRotTestCase
.test_data
))
297 suite
.addTest(TestRunner(LogicalTestCase
.test_data
))
298 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
299 suite
.addTest(TestRunner(BranchTestCase
.test_data
))
301 runner
= unittest
.TextTestRunner()