src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.isa.all import ISA
  16 from soc.decoder.power_enums import Function, XER_bits
  17
  18
  19 from soc.simple.core import NonProductionCore
  20 from soc.experiment.compalu_multi import find_ok # hack
  21
  22 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  23                                                  check_sim_memory)
  24
  25 # test with ALU data and Logical data
  26 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  27 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  28 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  29 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  30 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  31 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  32
  33 def setup_regs(core, test):
  34
  35     # set up INT regfile, "direct" write (bypass rd/write ports)
  36     intregs = core.regs.int
  37     for i in range(32):
  38         yield intregs.regs[i].reg.eq(test.regs[i])
  39
  40     # set up CR regfile, "direct" write across all CRs
  41     cr = test.cr
  42     crregs = core.regs.cr
  43     #cr = int('{:32b}'.format(cr)[::-1], 2)
  44     print ("cr reg", hex(cr))
  45     for i in range(8):
  46         #j = 7-i
  47         cri = (cr>>(i*4)) & 0xf
  48         #cri = int('{:04b}'.format(cri)[::-1], 2)
  49         print ("cr reg", hex(cri), i,
  50                 crregs.regs[i].reg.shape())
  51         yield crregs.regs[i].reg.eq(cri)
  52
  53     # set up XER.  "direct" write (bypass rd/write ports)
  54     xregs = core.regs.xer
  55     print ("sprs", test.sprs)
  56     if special_sprs['XER'] in test.sprs:
  57         xer = test.sprs[special_sprs['XER']]
  58         sobit = xer[XER_bits['SO']].value
  59         yield xregs.regs[xregs.SO].reg.eq(sobit)
  60         cabit = xer[XER_bits['CA']].value
  61         ca32bit = xer[XER_bits['CA32']].value
  62         yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
  63         ovbit = xer[XER_bits['OV']].value
  64         ov32bit = xer[XER_bits['OV32']].value
  65         yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
  66     else:
  67         yield xregs.regs[xregs.SO].reg.eq(0)
  68         yield xregs.regs[xregs.OV].reg.eq(0)
  69         yield xregs.regs[xregs.CA].reg.eq(0)
  70
  71
  72 def set_issue(core, dec2, sim):
  73     yield core.issue_i.eq(1)
  74     yield
  75     yield core.issue_i.eq(0)
  76     while True:
  77         busy_o = yield core.busy_o
  78         if busy_o:
  79             break
  80         print("!busy",)
  81         yield
  82
  83
  84 def wait_for_busy_clear(cu):
  85     while True:
  86         busy_o = yield cu.busy_o
  87         if not busy_o:
  88             break
  89         print("busy",)
  90         yield
  91
  92
  93 class TestRunner(FHDLTestCase):
  94     def __init__(self, tst_data):
  95         super().__init__("run_all")
  96         self.test_data = tst_data
  97
  98     def run_all(self):
  99         m = Module()
 100         comb = m.d.comb
 101         instruction = Signal(32)
 102         ivalid_i = Signal()
 103
 104         m.submodules.core = core = NonProductionCore()
 105         pdecode2 = core.pdecode2
 106         l0 = core.l0
 107
 108         comb += core.raw_opcode_i.eq(instruction)
 109         comb += core.ivalid_i.eq(ivalid_i)
 110
 111         # temporary hack: says "go" immediately for both address gen and ST
 112         ldst = core.fus.fus['ldst0']
 113         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
 114         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
 115
 116         # nmigen Simulation
 117         sim = Simulator(m)
 118         sim.add_clock(1e-6)
 119
 120         def process():
 121             yield core.issue_i.eq(0)
 122             yield
 123
 124             for test in self.test_data:
 125                 print(test.name)
 126                 program = test.program
 127                 self.subTest(test.name)
 128                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 129                           test.msr)
 130                 gen = program.generate_instructions()
 131                 instructions = list(zip(gen, program.assembly.splitlines()))
 132
 133                 yield from setup_test_memory(l0, sim)
 134                 yield from setup_regs(core, test)
 135
 136                 index = sim.pc.CIA.value//4
 137                 while index < len(instructions):
 138                     ins, code = instructions[index]
 139
 140                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 141                     print(code)
 142
 143                     # ask the decoder to decode this binary data (endian'd)
 144                     yield core.bigendian_i.eq(0)  # little / big?
 145                     yield instruction.eq(ins)          # raw binary instr.
 146                     yield ivalid_i.eq(1)
 147                     yield Settle()
 148                     #fn_unit = yield pdecode2.e.fn_unit
 149                     #fuval = self.funit.value
 150                     #self.assertEqual(fn_unit & fuval, fuval)
 151
 152                     # XER
 153                     so = yield xregs.regs[xregs.SO].reg
 154                     ov = yield xregs.regs[xregs.OV].reg
 155                     ca = yield xregs.regs[xregs.CA].reg
 156                     oe = yield pdecode2.e.oe.oe
 157                     oe_ok = yield pdecode2.e.oe.oe_ok
 158
 159                     print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 160                     print ("oe:", oe, oe_ok)
 161
 162                     # set operand and get inputs
 163                     yield from set_issue(core, pdecode2, sim)
 164                     yield Settle()
 165
 166                     yield from wait_for_busy_clear(core)
 167                     yield ivalid_i.eq(0)
 168                     yield
 169
 170                     print ("sim", code)
 171                     # call simulated operation
 172                     opname = code.split(' ')[0]
 173                     yield from sim.call(opname)
 174                     index = sim.pc.CIA.value//4
 175
 176                     # int regs
 177                     intregs = []
 178                     for i in range(32):
 179                         rval = yield core.regs.int.regs[i].reg
 180                         intregs.append(rval)
 181                     print ("int regs", list(map(hex, intregs)))
 182                     for i in range(32):
 183                         simregval = sim.gpr[i].asint()
 184                         self.assertEqual(simregval, intregs[i],
 185                             "int reg %d not equal %s" % (i, repr(code)))
 186
 187                     # CRs
 188                     crregs = []
 189                     for i in range(8):
 190                         rval = yield core.regs.cr.regs[i].reg
 191                         crregs.append(rval)
 192                     print ("cr regs", list(map(hex, crregs)))
 193                     print ("sim cr reg", hex(cr))
 194                     for i in range(8):
 195                         rval = crregs[i]
 196                         cri = sim.crl[7-i].get_range().value
 197                         print ("cr reg", i, hex(cri), i, hex(rval))
 198                         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 199                         self.assertEqual(cri, rval,
 200                             "cr reg %d not equal %s" % (i, repr(code)))
 201
 202                     # XER
 203                     so = yield xregs.regs[xregs.SO].reg
 204                     ov = yield xregs.regs[xregs.OV].reg
 205                     ca = yield xregs.regs[xregs.CA].reg
 206
 207                     print ("sim SO", sim.spr['XER'][XER_bits['SO']])
 208                     e_so = sim.spr['XER'][XER_bits['SO']].value
 209                     e_ov = sim.spr['XER'][XER_bits['OV']].value
 210                     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 211                     e_ca = sim.spr['XER'][XER_bits['CA']].value
 212                     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 213
 214                     e_ov = e_ov | (e_ov32<<1)
 215                     e_ca = e_ca | (e_ca32<<1)
 216
 217                     print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 218                     self.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 219                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 220                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 221
 222                     # Memory check
 223                     yield from check_sim_memory(self, l0, sim, code)
 224
 225         sim.add_sync_process(process)
 226         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 227                             traces=[]):
 228             sim.run()
 229
 230
 231 if __name__ == "__main__":
 232     unittest.main(exit=False)
 233     suite = unittest.TestSuite()
 234     suite.addTest(TestRunner(LDSTTestCase.test_data))
 235     suite.addTest(TestRunner(CRTestCase.test_data))
 236     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 237     suite.addTest(TestRunner(LogicalTestCase.test_data))
 238     suite.addTest(TestRunner(ALUTestCase.test_data))
 239     suite.addTest(TestRunner(BranchTestCase.test_data))
 240
 241     runner = unittest.TextTestRunner()
 242     runner.run(suite)
 243