1 from nmigen
import Module
, Signal
, Cat
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import special_sprs
7 from soc
.decoder
.power_decoder
import create_pdecode
8 from soc
.decoder
.power_decoder2
import PowerDecode2
9 from soc
.decoder
.isa
.all
import ISA
10 from soc
.decoder
.power_enums
import Function
, XER_bits
13 from soc
.simple
.core
import NonProductionCore
14 from soc
.experiment
.compalu_multi
import find_ok
# hack
16 # test with ALU data and Logical data
17 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
18 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
19 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
20 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
23 def set_cu_input(cu
, idx
, data
):
24 rdop
= cu
.get_in_name(idx
)
25 yield cu
.src_i
[idx
].eq(data
)
27 rd_rel_o
= yield cu
.rd
.rel
[idx
]
28 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
32 yield cu
.rd
.go
[idx
].eq(1)
35 rd_rel_o
= yield cu
.rd
.rel
[idx
]
38 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
40 yield cu
.rd
.go
[idx
].eq(0)
41 yield cu
.src_i
[idx
].eq(0)
44 def get_cu_output(cu
, idx
, code
):
45 wrmask
= yield cu
.wrmask
46 wrop
= cu
.get_out_name(idx
)
47 wrok
= cu
.get_out(idx
)
48 fname
= find_ok(wrok
.fields
)
49 wrok
= yield getattr(wrok
, fname
)
50 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
51 assert wrmask
& (1<<idx
), \
52 "get_cu_output '%s': mask bit %d not set\n" \
53 "write-operand '%s' Data.ok likely not set (%s)" \
54 % (code
, idx
, wrop
, hex(wrok
))
56 wr_relall_o
= yield cu
.wr
.rel
57 wr_rel_o
= yield cu
.wr
.rel
[idx
]
58 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
62 yield cu
.wr
.go
[idx
].eq(1)
64 result
= yield cu
.dest
[idx
]
66 yield cu
.wr
.go
[idx
].eq(0)
67 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
71 def set_cu_inputs(cu
, inp
):
72 for idx
, data
in inp
.items():
73 yield from set_cu_input(cu
, idx
, data
)
76 def set_issue(core
, dec2
, sim
):
77 yield core
.issue_i
.eq(1)
79 yield core
.issue_i
.eq(0)
81 busy_o
= yield core
.busy_o
88 def wait_for_busy_clear(cu
):
90 busy_o
= yield cu
.busy_o
97 def get_cu_outputs(cu
, code
):
99 for i
in range(cu
.n_dst
):
100 wr_rel_o
= yield cu
.wr
.rel
[i
]
102 result
= yield from get_cu_output(cu
, i
, code
)
103 wrop
= cu
.get_out_name(i
)
104 print ("output", i
, wrop
, hex(result
))
109 def get_inp_indexed(cu
, inp
):
111 for i
in range(cu
.n_src
):
112 wrop
= cu
.get_in_name(i
)
118 class TestRunner(FHDLTestCase
):
119 def __init__(self
, tst_data
):
120 super().__init
__("run_all")
121 self
.test_data
= tst_data
126 instruction
= Signal(32)
129 m
.submodules
.core
= core
= NonProductionCore()
130 pdecode
= core
.pdecode
131 pdecode2
= core
.pdecode2
133 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
134 comb
+= core
.ivalid_i
.eq(ivalid_i
)
140 yield core
.issue_i
.eq(0)
143 for test
in self
.test_data
:
145 program
= test
.program
146 self
.subTest(test
.name
)
147 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
)
148 gen
= program
.generate_instructions()
149 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
151 # set up INT regfile, "direct" write (bypass rd/write ports)
153 yield core
.regs
.int.regs
[i
].reg
.eq(test
.regs
[i
])
155 # set up CR regfile, "direct" write across all CRs
157 print ("cr reg", hex(cr
))
159 cri
= (cr
>>(j
*4)) & 0xf
160 print ("cr reg", hex(cri
), i
,
161 core
.regs
.cr
.regs
[i
].reg
.shape())
162 yield core
.regs
.cr
.regs
[i
].reg
.eq(cri
)
164 # set up XER. "direct" write (bypass rd/write ports)
165 xregs
= core
.regs
.xer
166 print ("sprs", test
.sprs
)
167 if special_sprs
['XER'] in test
.sprs
:
168 xer
= test
.sprs
[special_sprs
['XER']]
169 sobit
= xer
[XER_bits
['SO']].asint()
170 yield xregs
.regs
[xregs
.SO
].reg
.eq(sobit
)
171 cabit
= xer
[XER_bits
['CA']].asint()
172 ca32bit
= xer
[XER_bits
['CA32']].asint()
173 yield xregs
.regs
[xregs
.CA
].reg
.eq(Cat(cabit
, ca32bit
))
174 ovbit
= xer
[XER_bits
['OV']].asint()
175 ov32bit
= xer
[XER_bits
['OV32']].asint()
176 yield xregs
.regs
[xregs
.OV
].reg
.eq(Cat(ovbit
, ov32bit
))
178 yield xregs
.regs
[xregs
.SO
].reg
.eq(0)
179 yield xregs
.regs
[xregs
.OV
].reg
.eq(0)
180 yield xregs
.regs
[xregs
.CA
].reg
.eq(0)
182 index
= sim
.pc
.CIA
.value
//4
183 while index
< len(instructions
):
184 ins
, code
= instructions
[index
]
186 print("0x{:X}".format(ins
& 0xffffffff))
189 # ask the decoder to decode this binary data (endian'd)
190 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
191 yield instruction
.eq(ins
) # raw binary instr.
194 #fn_unit = yield pdecode2.e.fn_unit
195 #fuval = self.funit.value
196 #self.assertEqual(fn_unit & fuval, fuval)
198 # set operand and get inputs
199 yield from set_issue(core
, pdecode2
, sim
)
202 yield from wait_for_busy_clear(core
)
207 # call simulated operation
208 opname
= code
.split(' ')[0]
209 yield from sim
.call(opname
)
210 index
= sim
.pc
.CIA
.value
//4
215 rval
= yield core
.regs
.int.regs
[i
].reg
217 print ("int regs", list(map(hex, intregs
)))
219 simregval
= sim
.gpr
[i
].asint()
220 self
.assertEqual(simregval
, intregs
[i
],
221 "int reg %d not equal %s" % (i
, repr(code
)))
223 sim
.add_sync_process(process
)
224 with sim
.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
229 if __name__
== "__main__":
230 unittest
.main(exit
=False)
231 suite
= unittest
.TestSuite()
232 suite
.addTest(TestRunner(CRTestCase
.test_data
))
233 #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
234 #suite.addTest(TestRunner(LogicalTestCase.test_data))
235 #suite.addTest(TestRunner(ALUTestCase.test_data))
237 runner
= unittest
.TextTestRunner()