src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.isa.all import ISA
  16 from soc.decoder.power_enums import Function, XER_bits
  17
  18
  19 from soc.simple.core import NonProductionCore
  20 from soc.experiment.compalu_multi import find_ok # hack
  21
  22 # test with ALU data and Logical data
  23 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  24 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  25 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  26 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  27 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  28
  29
  30 def set_issue(core, dec2, sim):
  31     yield core.issue_i.eq(1)
  32     yield
  33     yield core.issue_i.eq(0)
  34     while True:
  35         busy_o = yield core.busy_o
  36         if busy_o:
  37             break
  38         print("!busy",)
  39         yield
  40
  41
  42 def wait_for_busy_clear(cu):
  43     while True:
  44         busy_o = yield cu.busy_o
  45         if not busy_o:
  46             break
  47         print("busy",)
  48         yield
  49
  50
  51 class TestRunner(FHDLTestCase):
  52     def __init__(self, tst_data):
  53         super().__init__("run_all")
  54         self.test_data = tst_data
  55
  56     def run_all(self):
  57         m = Module()
  58         comb = m.d.comb
  59         instruction = Signal(32)
  60         ivalid_i = Signal()
  61
  62         m.submodules.core = core = NonProductionCore()
  63         pdecode = core.pdecode
  64         pdecode2 = core.pdecode2
  65
  66         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  67         comb += core.ivalid_i.eq(ivalid_i)
  68         sim = Simulator(m)
  69
  70         sim.add_clock(1e-6)
  71
  72         def process():
  73             yield core.issue_i.eq(0)
  74             yield
  75
  76             for test in self.test_data:
  77                 print(test.name)
  78                 program = test.program
  79                 self.subTest(test.name)
  80                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
  81                           test.msr)
  82                 gen = program.generate_instructions()
  83                 instructions = list(zip(gen, program.assembly.splitlines()))
  84
  85                 # set up INT regfile, "direct" write (bypass rd/write ports)
  86                 for i in range(32):
  87                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
  88
  89                 # set up CR regfile, "direct" write across all CRs
  90                 cr = test.cr
  91                 #cr = int('{:32b}'.format(cr)[::-1], 2)
  92                 print ("cr reg", hex(cr))
  93                 for i in range(8):
  94                     #j = 7-i
  95                     cri = (cr>>(i*4)) & 0xf
  96                     #cri = int('{:04b}'.format(cri)[::-1], 2)
  97                     print ("cr reg", hex(cri), i,
  98                             core.regs.cr.regs[i].reg.shape())
  99                     yield core.regs.cr.regs[i].reg.eq(cri)
 100
 101                 # set up XER.  "direct" write (bypass rd/write ports)
 102                 xregs = core.regs.xer
 103                 print ("sprs", test.sprs)
 104                 if special_sprs['XER'] in test.sprs:
 105                     xer = test.sprs[special_sprs['XER']]
 106                     sobit = 1 if xer[XER_bits['SO']] else 0
 107                     yield xregs.regs[xregs.SO].reg.eq(sobit)
 108                     cabit = 1 if xer[XER_bits['CA']] else 0
 109                     ca32bit = 1 if xer[XER_bits['CA32']] else 0
 110                     yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
 111                     ovbit = 1 if xer[XER_bits['OV']] else 0
 112                     ov32bit = 1 if xer[XER_bits['OV32']] else 0
 113                     yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
 114                 else:
 115                     yield xregs.regs[xregs.SO].reg.eq(0)
 116                     yield xregs.regs[xregs.OV].reg.eq(0)
 117                     yield xregs.regs[xregs.CA].reg.eq(0)
 118
 119                 index = sim.pc.CIA.value//4
 120                 while index < len(instructions):
 121                     ins, code = instructions[index]
 122
 123                     print("0x{:X}".format(ins & 0xffffffff))
 124                     print(code)
 125
 126                     # ask the decoder to decode this binary data (endian'd)
 127                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 128                     yield instruction.eq(ins)          # raw binary instr.
 129                     yield ivalid_i.eq(1)
 130                     yield Settle()
 131                     #fn_unit = yield pdecode2.e.fn_unit
 132                     #fuval = self.funit.value
 133                     #self.assertEqual(fn_unit & fuval, fuval)
 134
 135                     # set operand and get inputs
 136                     yield from set_issue(core, pdecode2, sim)
 137                     yield Settle()
 138
 139                     yield from wait_for_busy_clear(core)
 140                     yield ivalid_i.eq(0)
 141                     yield
 142
 143                     print ("sim", code)
 144                     # call simulated operation
 145                     opname = code.split(' ')[0]
 146                     yield from sim.call(opname)
 147                     index = sim.pc.CIA.value//4
 148
 149                     # int regs
 150                     intregs = []
 151                     for i in range(32):
 152                         rval = yield core.regs.int.regs[i].reg
 153                         intregs.append(rval)
 154                     print ("int regs", list(map(hex, intregs)))
 155                     for i in range(32):
 156                         simregval = sim.gpr[i].asint()
 157                         self.assertEqual(simregval, intregs[i],
 158                             "int reg %d not equal %s" % (i, repr(code)))
 159
 160                     # CRs
 161                     crregs = []
 162                     for i in range(8):
 163                         rval = yield core.regs.cr.regs[i].reg
 164                         crregs.append(rval)
 165                     print ("cr regs", list(map(hex, crregs)))
 166                     print ("sim cr reg", hex(cr))
 167                     for i in range(8):
 168                         rval = crregs[i]
 169                         cri = sim.crl[7-i].get_range().value
 170                         print ("cr reg", i, hex(cri), i, hex(rval))
 171                         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 172                         self.assertEqual(cri, rval,
 173                             "cr reg %d not equal %s" % (i, repr(code)))
 174
 175                     # XER
 176                     so = yield xregs.regs[xregs.SO].reg
 177                     ov = yield xregs.regs[xregs.OV].reg
 178                     ca = yield xregs.regs[xregs.CA].reg
 179
 180                     e_so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 181                     e_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 182                     e_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 183                     e_ca = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 184                     e_ca32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 185
 186                     e_ov = e_ov | (e_ov32<<1)
 187                     e_ca = e_ca | (e_ca32<<1)
 188
 189                     self.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 190                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 191                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 192
 193         sim.add_sync_process(process)
 194         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 195                             traces=[]):
 196             sim.run()
 197
 198
 199 if __name__ == "__main__":
 200     unittest.main(exit=False)
 201     suite = unittest.TestSuite()
 202     #suite.addTest(TestRunner(CRTestCase.test_data))
 203     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 204     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 205     suite.addTest(TestRunner(ALUTestCase.test_data))
 206     #suite.addTest(TestRunner(BranchTestCase.test_data))
 207
 208     runner = unittest.TextTestRunner()
 209     runner.run(suite)
 210