3d1359ea004c9faf3bfb82330416a4433f6b280d
[soc.git] / src / soc / simple / test / test_issuer.py
1 """simple core test, runs instructions from a TestMemory
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7 from nmigen import Module, Signal, Cat
8
9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
11 from nmutil.sim_tmp_alternative import Simulator, Settle
12
13 from nmutil.formaltest import FHDLTestCase
14 from nmigen.cli import rtlil
15 import unittest
16 from soc.decoder.isa.caller import special_sprs
17 from soc.decoder.isa.all import ISA
18 from soc.decoder.power_enums import Function, XER_bits
19 from soc.config.endian import bigendian
20
21 from soc.decoder.power_decoder import create_pdecode
22 from soc.decoder.power_decoder2 import PowerDecode2
23
24 from soc.simple.issuer import TestIssuerInternal
25 from soc.experiment.compalu_multi import find_ok # hack
26
27 from soc.config.test.test_loadstore import TestMemPspec
28 from soc.simple.test.test_core import (setup_regs, check_regs,
29 wait_for_busy_clear,
30 wait_for_busy_hi)
31 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
32 check_sim_memory)
33 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
34
35 # test with ALU data and Logical data
36 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
37 from soc.fu.div.test.test_pipe_caller import DivTestCases
38 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
39 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
40 from soc.fu.cr.test.test_pipe_caller import CRTestCase
41 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
42 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
43 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
44 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
45 #from soc.simulator.test_helloworld_sim import HelloTestCases
46
47
48 def setup_i_memory(imem, startaddr, instructions):
49 mem = imem
50 print("insn before, init mem", mem.depth, mem.width, mem,
51 len(instructions))
52 for i in range(mem.depth):
53 yield mem._array[i].eq(0)
54 yield Settle()
55 startaddr //= 4 # instructions are 32-bit
56 if mem.width == 32:
57 mask = ((1 << 32)-1)
58 for ins in instructions:
59 if isinstance(ins, tuple):
60 insn, code = ins
61 else:
62 insn, code = ins, ''
63 insn = insn & 0xffffffff
64 yield mem._array[startaddr].eq(insn)
65 yield Settle()
66 if insn != 0:
67 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
68 startaddr += 1
69 startaddr = startaddr & mask
70 return
71
72 # 64 bit
73 mask = ((1 << 64)-1)
74 for ins in instructions:
75 if isinstance(ins, tuple):
76 insn, code = ins
77 else:
78 insn, code = ins, ''
79 insn = insn & 0xffffffff
80 msbs = (startaddr >> 1) & mask
81 val = yield mem._array[msbs]
82 if insn != 0:
83 print("before set", hex(4*startaddr),
84 hex(msbs), hex(val), hex(insn))
85 lsb = 1 if (startaddr & 1) else 0
86 val = (val | (insn << (lsb*32)))
87 val = val & mask
88 yield mem._array[msbs].eq(val)
89 yield Settle()
90 if insn != 0:
91 print("after set", hex(4*startaddr), hex(msbs), hex(val))
92 print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
93 startaddr += 1
94 startaddr = startaddr & mask
95
96
97 def set_dmi(dmi, addr, data):
98 yield dmi.req_i.eq(1)
99 yield dmi.addr_i.eq(addr)
100 yield dmi.din.eq(data)
101 yield dmi.we_i.eq(1)
102 while True:
103 ack = yield dmi.ack_o
104 if ack:
105 break
106 yield
107 yield
108 yield dmi.req_i.eq(0)
109 yield dmi.addr_i.eq(0)
110 yield dmi.din.eq(0)
111 yield dmi.we_i.eq(0)
112 yield
113
114
115 def get_dmi(dmi, addr):
116 yield dmi.req_i.eq(1)
117 yield dmi.addr_i.eq(addr)
118 yield dmi.din.eq(0)
119 yield dmi.we_i.eq(0)
120 while True:
121 ack = yield dmi.ack_o
122 if ack:
123 break
124 yield
125 yield # wait one
126 data = yield dmi.dout # get data after ack valid for 1 cycle
127 yield dmi.req_i.eq(0)
128 yield dmi.addr_i.eq(0)
129 yield dmi.we_i.eq(0)
130 yield
131 return data
132
133
134 class TestRunner(FHDLTestCase):
135 def __init__(self, tst_data):
136 super().__init__("run_all")
137 self.test_data = tst_data
138
139 def run_all(self):
140 m = Module()
141 comb = m.d.comb
142 pc_i = Signal(32)
143
144 pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
145 imem_ifacetype='test_bare_wb',
146 addr_wid=48,
147 mask_wid=8,
148 imem_reg_wid=64,
149 #wb_data_width=32,
150 reg_wid=64)
151 m.submodules.issuer = issuer = TestIssuerInternal(pspec)
152 imem = issuer.imem._get_memory()
153 core = issuer.core
154 dmi = issuer.dbg.dmi
155 pdecode2 = issuer.pdecode2
156 l0 = core.l0
157
158 # copy of the decoder for simulator
159 simdec = create_pdecode()
160 simdec2 = PowerDecode2(simdec)
161 m.submodules.simdec2 = simdec2 # pain in the neck
162
163 comb += issuer.pc_i.data.eq(pc_i)
164
165 # nmigen Simulation
166 sim = Simulator(m)
167 sim.add_clock(1e-6)
168
169 def process():
170
171 # start in stopped
172 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
173 yield
174 yield
175
176 for test in self.test_data:
177
178 # pull a reset
179 #yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
180
181 # set up bigendian (TODO: don't do this, use MSR)
182 yield issuer.core_bigendian_i.eq(bigendian)
183 yield Settle()
184
185 yield
186 yield
187 yield
188 yield
189
190 print(test.name)
191 program = test.program
192 self.subTest(test.name)
193 print("regs", test.regs)
194 print("sprs", test.sprs)
195 print("cr", test.cr)
196 print("mem", test.mem)
197 print("msr", test.msr)
198 print("assem", program.assembly)
199 gen = list(program.generate_instructions())
200 insncode = program.assembly.splitlines()
201 instructions = list(zip(gen, insncode))
202 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
203 test.msr,
204 initial_insns=gen, respect_pc=True,
205 disassembly=insncode,
206 bigendian=bigendian)
207
208 pc = 0 # start address
209 counter = 0 # test to pause/start
210
211 yield from setup_i_memory(imem, pc, instructions)
212 yield from setup_test_memory(l0, sim)
213 yield from setup_regs(pdecode2, core, test)
214
215 yield pc_i.eq(pc)
216 yield issuer.pc_i.ok.eq(1)
217 yield
218
219 print("instructions", instructions)
220
221 index = sim.pc.CIA.value//4
222 while index < len(instructions):
223 ins, code = instructions[index]
224
225 print("instruction: 0x{:X}".format(ins & 0xffffffff))
226 print(index, code)
227
228 if counter == 0:
229 # start the core
230 yield
231 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
232 yield issuer.pc_i.ok.eq(0) # no change PC after this
233 yield
234 yield
235
236 counter = counter + 1
237
238 # wait until executed
239 yield from wait_for_busy_hi(core)
240 yield from wait_for_busy_clear(core)
241
242 # set up simulated instruction (in simdec2)
243 try:
244 yield from sim.setup_one()
245 except KeyError: # indicates instruction not in imem: stop
246 break
247 yield Settle()
248
249 # call simulated operation
250 print("sim", code)
251 yield from sim.execute_one()
252 yield Settle()
253 index = sim.pc.CIA.value//4
254
255 terminated = yield issuer.dbg.terminated_o
256 print("terminated", terminated)
257
258 if index >= len(instructions):
259 print ("index over, send dmi stop")
260 # stop at end
261 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
262 yield
263 yield
264
265 # wait one cycle for registers to settle
266 yield
267
268 # register check
269 yield from check_regs(self, sim, core, test, code)
270
271 # Memory check
272 yield from check_sim_memory(self, l0, sim, code)
273
274 terminated = yield issuer.dbg.terminated_o
275 print("terminated(2)", terminated)
276 if terminated:
277 break
278
279 # stop at end
280 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
281 yield
282 yield
283
284 # get CR
285 cr = yield from get_dmi(dmi, DBGCore.CR)
286 print ("after test %s cr value %x" % (test.name, cr))
287
288 # get XER
289 xer = yield from get_dmi(dmi, DBGCore.XER)
290 print ("after test %s XER value %x" % (test.name, xer))
291
292 # test of dmi reg get
293 for int_reg in range(32):
294 yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
295 value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
296
297 print ("after test %s reg %2d value %x" % \
298 (test.name, int_reg, value))
299
300 sim.add_sync_process(process)
301 with sim.write_vcd("issuer_simulator.vcd",
302 traces=[]):
303 sim.run()
304
305
306 if __name__ == "__main__":
307 unittest.main(exit=False)
308 suite = unittest.TestSuite()
309 # suite.addTest(TestRunner(HelloTestCases.test_data))
310 suite.addTest(TestRunner(DivTestCases().test_data))
311 # suite.addTest(TestRunner(AttnTestCase.test_data))
312 suite.addTest(TestRunner(GeneralTestCases.test_data))
313 suite.addTest(TestRunner(LDSTTestCase().test_data))
314 suite.addTest(TestRunner(CRTestCase().test_data))
315 suite.addTest(TestRunner(ShiftRotTestCase().test_data))
316 suite.addTest(TestRunner(LogicalTestCase().test_data))
317 suite.addTest(TestRunner(ALUTestCase().test_data))
318 # suite.addTest(TestRunner(BranchTestCase.test_data))
319 # suite.addTest(TestRunner(SPRTestCase.test_data))
320
321 runner = unittest.TextTestRunner()
322 runner.run(suite)