1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
23 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
26 # test with ALU data and Logical data
27 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
28 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
29 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
30 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
31 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
32 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
33 from soc
.simulator
.test_sim
import GeneralTestCases
36 def setup_i_memory(imem
, startaddr
, instructions
):
38 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
)
39 for i
in range(mem
.depth
):
40 yield mem
._array
[i
].eq(0)
42 startaddr
//= 4 # instructions are 32-bit
44 for insn
, code
in instructions
:
45 msbs
= (startaddr
>>1) & mask
46 val
= yield mem
._array
[msbs
]
47 print ("before set", hex(startaddr
), hex(msbs
), hex(val
))
48 lsb
= 1 if (startaddr
& 1) else 0
49 val
= (val |
(insn
<< (lsb
*32))) & mask
50 yield mem
._array
[msbs
].eq(val
)
52 print ("after set", hex(startaddr
), hex(msbs
), hex(val
))
53 print ("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
55 startaddr
= startaddr
& mask
58 class TestRunner(FHDLTestCase
):
59 def __init__(self
, tst_data
):
60 super().__init
__("run_all")
61 self
.test_data
= tst_data
69 m
.submodules
.issuer
= issuer
= TestIssuer(ifacetype
="test_bare_wb")
70 imem
= issuer
.imem
.mem
.mem
72 pdecode2
= core
.pdecode2
75 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
76 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
84 for test
in self
.test_data
:
86 program
= test
.program
87 self
.subTest(test
.name
)
88 print ("regs", test
.regs
)
89 print ("sprs", test
.sprs
)
91 print ("mem", test
.mem
)
92 print ("msr", test
.msr
)
93 print ("assem", program
.assembly
)
94 gen
= list(program
.generate_instructions())
95 insncode
= program
.assembly
.splitlines()
96 instructions
= list(zip(gen
, insncode
))
97 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
99 initial_insns
=gen
, respect_pc
=True,
100 disassembly
=insncode
)
102 pc
= 0 # start address
104 yield from setup_i_memory(imem
, pc
, instructions
)
105 yield from setup_test_memory(l0
, sim
)
106 yield from setup_regs(core
, test
)
109 yield issuer
.pc_i
.ok
.eq(1)
111 index
= sim
.pc
.CIA
.value
//4
112 while index
< len(instructions
):
113 ins
, code
= instructions
[index
]
115 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
118 # start the instruction
119 yield go_insn_i
.eq(1)
121 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
122 yield go_insn_i
.eq(0) # and don't issue a new insn
124 # wait until executed
125 yield from wait_for_busy_hi(core
)
126 yield from wait_for_busy_clear(core
)
129 # call simulated operation
130 opname
= code
.split(' ')[0]
131 yield from sim
.call(opname
)
133 index
= sim
.pc
.CIA
.value
//4
136 yield from check_regs(self
, sim
, core
, test
, code
)
139 yield from check_sim_memory(self
, l0
, sim
, code
)
141 sim
.add_sync_process(process
)
142 with sim
.write_vcd("issuer_simulator.vcd",
147 if __name__
== "__main__":
148 unittest
.main(exit
=False)
149 suite
= unittest
.TestSuite()
150 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
151 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
152 suite
.addTest(TestRunner(CRTestCase
.test_data
))
153 suite
.addTest(TestRunner(ShiftRotTestCase
.test_data
))
154 suite
.addTest(TestRunner(LogicalTestCase
.test_data
))
155 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
156 suite
.addTest(TestRunner(BranchTestCase
.test_data
))
158 runner
= unittest
.TextTestRunner()