b6cc9f6edc66294219826125fb506e0eb2d41c5b
1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
23 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
26 # test with ALU data and Logical data
27 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
28 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
29 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
30 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
31 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
32 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
33 from soc
.simulator
.test_sim
import GeneralTestCases
36 def setup_i_memory(imem
, startaddr
, instructions
):
38 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
)
39 for i
in range(mem
.depth
):
40 yield mem
._array
[i
].eq(0)
41 startaddr
//= 4 # assume i-mem is 32-bit wide
42 for insn
, code
in instructions
:
43 print ("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
44 yield mem
._array
[startaddr
].eq(insn
)
48 class TestRunner(FHDLTestCase
):
49 def __init__(self
, tst_data
):
50 super().__init
__("run_all")
51 self
.test_data
= tst_data
59 m
.submodules
.issuer
= issuer
= TestIssuer(ifacetype
="test_bare_wb")
60 imem
= issuer
.imem
.mem
62 pdecode2
= core
.pdecode2
65 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
66 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
74 for test
in self
.test_data
:
76 program
= test
.program
77 self
.subTest(test
.name
)
78 print ("regs", test
.regs
)
79 print ("sprs", test
.sprs
)
81 print ("mem", test
.mem
)
82 print ("msr", test
.msr
)
83 print ("assem", program
.assembly
)
84 gen
= list(program
.generate_instructions())
85 insncode
= program
.assembly
.splitlines()
86 instructions
= list(zip(gen
, insncode
))
87 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
89 initial_insns
=gen
, respect_pc
=True,
92 pc
= 0 # start address
94 yield from setup_i_memory(imem
, pc
, instructions
)
95 yield from setup_test_memory(l0
, sim
)
96 yield from setup_regs(core
, test
)
99 yield issuer
.pc_i
.ok
.eq(1)
101 index
= sim
.pc
.CIA
.value
//4
102 while index
< len(instructions
):
103 ins
, code
= instructions
[index
]
105 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
108 # start the instruction
109 yield go_insn_i
.eq(1)
111 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
112 yield go_insn_i
.eq(0) # and don't issue a new insn
114 # wait until executed
115 yield from wait_for_busy_hi(core
)
116 yield from wait_for_busy_clear(core
)
119 # call simulated operation
120 opname
= code
.split(' ')[0]
121 yield from sim
.call(opname
)
123 index
= sim
.pc
.CIA
.value
//4
126 yield from check_regs(self
, sim
, core
, test
, code
)
129 yield from check_sim_memory(self
, l0
, sim
, code
)
131 sim
.add_sync_process(process
)
132 with sim
.write_vcd("issuer_simulator.vcd",
137 if __name__
== "__main__":
138 unittest
.main(exit
=False)
139 suite
= unittest
.TestSuite()
140 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
141 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
142 suite
.addTest(TestRunner(CRTestCase
.test_data
))
143 suite
.addTest(TestRunner(ShiftRotTestCase
.test_data
))
144 suite
.addTest(TestRunner(LogicalTestCase
.test_data
))
145 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
146 suite
.addTest(TestRunner(BranchTestCase
.test_data
))
148 runner
= unittest
.TextTestRunner()