src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15
  16
  17 from soc.simple.core import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok # hack
  19
  20 from soc.simple.test.test_core import (setup_regs, check_regs,
  21                                        wait_for_busy_clear,
  22                                        wait_for_busy_hi)
  23 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  24                                                  check_sim_memory)
  25
  26 # test with ALU data and Logical data
  27 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  28 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  29 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  30 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  31 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  32 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  33
  34
  35 def setup_i_memory(imem, startaddr, instructions):
  36     mem = imem
  37     print ("insn before, init mem", mem.depth, mem.width, mem)
  38     for i in range(mem.depth):
  39         yield mem._array[i].eq(0)
  40     startaddr //= 4 # assume i-mem is 32-bit wide
  41     for insn, code in instructions:
  42         print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  43         yield mem._array[startaddr].eq(insn)
  44         startaddr += 1
  45
  46
  47 class TestRunner(FHDLTestCase):
  48     def __init__(self, tst_data):
  49         super().__init__("run_all")
  50         self.test_data = tst_data
  51
  52     def run_all(self):
  53         m = Module()
  54         comb = m.d.comb
  55         go_insn_i = Signal()
  56
  57         m.submodules.issuer = issuer = TestIssuer()
  58         imem = issuer.imem.mem
  59         core = issuer.core
  60         pdecode2 = core.pdecode2
  61         l0 = core.l0
  62
  63         comb += issuer.go_insn_i.eq(go_insn_i)
  64
  65         # nmigen Simulation
  66         sim = Simulator(m)
  67         sim.add_clock(1e-6)
  68
  69         def process():
  70
  71             for test in self.test_data:
  72                 print(test.name)
  73                 program = test.program
  74                 self.subTest(test.name)
  75                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
  76                           test.msr)
  77                 gen = program.generate_instructions()
  78                 instructions = list(zip(gen, program.assembly.splitlines()))
  79
  80                 pc = 0 # start address
  81
  82                 yield from setup_i_memory(imem, pc, instructions)
  83                 yield from setup_test_memory(l0, sim)
  84                 yield from setup_regs(core, test)
  85
  86                 yield issuer.pc_i.data.eq(pc)
  87                 yield issuer.pc_i.ok.eq(1)
  88
  89                 index = sim.pc.CIA.value//4
  90                 while index < len(instructions):
  91                     ins, code = instructions[index]
  92
  93                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
  94                     print(code)
  95
  96                     # start the instruction
  97                     yield go_insn_i.eq(1)
  98                     yield
  99                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 100                     yield go_insn_i.eq(0)      # and don't issue a new insn
 101
 102                     # wait until executed
 103                     yield from wait_for_busy_hi(core)
 104                     yield from wait_for_busy_clear(core)
 105
 106                     print ("sim", code)
 107                     # call simulated operation
 108                     opname = code.split(' ')[0]
 109                     yield from sim.call(opname)
 110                     index = sim.pc.CIA.value//4
 111
 112                     # register check
 113                     yield from check_regs(self, sim, core, test, code)
 114
 115                     # Memory check
 116                     yield from check_sim_memory(self, l0, sim, code)
 117
 118         sim.add_sync_process(process)
 119         with sim.write_vcd("issuer_simulator.vcd",
 120                             traces=[]):
 121             sim.run()
 122
 123
 124 if __name__ == "__main__":
 125     unittest.main(exit=False)
 126     suite = unittest.TestSuite()
 127     #suite.addTest(TestRunner(LDSTTestCase.test_data))
 128     #suite.addTest(TestRunner(CRTestCase.test_data))
 129     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 130     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 131     suite.addTest(TestRunner(ALUTestCase.test_data))
 132     #suite.addTest(TestRunner(BranchTestCase.test_data))
 133
 134     runner = unittest.TextTestRunner()
 135     runner.run(suite)
 136