src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15
  16
  17 from soc.simple.issuer import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok # hack
  19
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.simple.test.test_core import (setup_regs, check_regs,
  22                                        wait_for_busy_clear,
  23                                        wait_for_busy_hi)
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26
  27 # test with ALU data and Logical data
  28 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  29 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  30 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  31 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  32 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  33 from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  34 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  35 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  36
  37
  38 def setup_i_memory(imem, startaddr, instructions):
  39     mem = imem
  40     print ("insn before, init mem", mem.depth, mem.width, mem)
  41     for i in range(mem.depth):
  42         yield mem._array[i].eq(0)
  43     yield Settle()
  44     startaddr //= 4 # instructions are 32-bit
  45     mask = ((1<<64)-1)
  46     for insn, code in instructions:
  47         msbs = (startaddr>>1) & mask
  48         val = yield mem._array[msbs]
  49         print ("before set", hex(startaddr), hex(msbs), hex(val))
  50         lsb = 1 if (startaddr & 1) else 0
  51         val = (val | (insn << (lsb*32))) & mask
  52         yield mem._array[msbs].eq(val)
  53         yield Settle()
  54         print ("after  set", hex(startaddr), hex(msbs), hex(val))
  55         print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  56         startaddr += 1
  57         startaddr = startaddr & mask
  58
  59
  60 class TestRunner(FHDLTestCase):
  61     def __init__(self, tst_data):
  62         super().__init__("run_all")
  63         self.test_data = tst_data
  64
  65     def run_all(self):
  66         m = Module()
  67         comb = m.d.comb
  68         go_insn_i = Signal()
  69         pc_i = Signal(32)
  70
  71         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  72                              imem_ifacetype='test_bare_wb',
  73                              addr_wid=48,
  74                              mask_wid=8,
  75                              reg_wid=64)
  76         m.submodules.issuer = issuer = TestIssuer(pspec)
  77         imem = issuer.imem._get_memory()
  78         core = issuer.core
  79         pdecode2 = core.pdecode2
  80         l0 = core.l0
  81
  82         comb += issuer.pc_i.data.eq(pc_i)
  83         comb += issuer.go_insn_i.eq(go_insn_i)
  84
  85         # nmigen Simulation
  86         sim = Simulator(m)
  87         sim.add_clock(1e-6)
  88
  89         def process():
  90
  91             for test in self.test_data:
  92
  93                 # get core going
  94                 yield core.core_start_i.eq(1)
  95                 yield
  96                 yield core.core_start_i.eq(0)
  97                 yield Settle()
  98
  99                 print(test.name)
 100                 program = test.program
 101                 self.subTest(test.name)
 102                 print ("regs", test.regs)
 103                 print ("sprs", test.sprs)
 104                 print ("cr", test.cr)
 105                 print ("mem", test.mem)
 106                 print ("msr", test.msr)
 107                 print ("assem", program.assembly)
 108                 gen = list(program.generate_instructions())
 109                 insncode = program.assembly.splitlines()
 110                 instructions = list(zip(gen, insncode))
 111                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 112                           test.msr,
 113                           initial_insns=gen, respect_pc=True,
 114                           disassembly=insncode)
 115
 116                 pc = 0 # start address
 117
 118                 yield from setup_i_memory(imem, pc, instructions)
 119                 yield from setup_test_memory(l0, sim)
 120                 yield from setup_regs(core, test)
 121
 122                 yield pc_i.eq(pc)
 123                 yield issuer.pc_i.ok.eq(1)
 124
 125                 index = sim.pc.CIA.value//4
 126                 while index < len(instructions):
 127                     ins, code = instructions[index]
 128
 129                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 130                     print(index, code)
 131
 132                     # start the instruction
 133                     yield go_insn_i.eq(1)
 134                     yield
 135                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 136                     yield go_insn_i.eq(0)      # and don't issue a new insn
 137                     yield Settle()
 138
 139                     # wait until executed
 140                     yield from wait_for_busy_hi(core)
 141                     yield from wait_for_busy_clear(core)
 142
 143                     print ("sim", code)
 144                     # call simulated operation
 145                     opname = code.split(' ')[0]
 146                     yield from sim.call(opname)
 147                     yield Settle()
 148                     index = sim.pc.CIA.value//4
 149
 150                     # register check
 151                     yield from check_regs(self, sim, core, test, code)
 152
 153                     # Memory check
 154                     yield from check_sim_memory(self, l0, sim, code)
 155
 156                     terminated = yield core.core_terminated_o
 157                     if terminated:
 158                         break
 159
 160         sim.add_sync_process(process)
 161         with sim.write_vcd("issuer_simulator.vcd",
 162                             traces=[]):
 163             sim.run()
 164
 165
 166 if __name__ == "__main__":
 167     unittest.main(exit=False)
 168     suite = unittest.TestSuite()
 169     suite.addTest(TestRunner(AttnTestCase.test_data))
 170     #suite.addTest(TestRunner(GeneralTestCases.test_data))
 171     #suite.addTest(TestRunner(LDSTTestCase.test_data))
 172     #suite.addTest(TestRunner(CRTestCase.test_data))
 173     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 174     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 175     suite.addTest(TestRunner(ALUTestCase.test_data))
 176     #suite.addTest(TestRunner(BranchTestCase.test_data))
 177     #suite.addTest(TestRunner(SPRTestCase.test_data))
 178
 179     runner = unittest.TextTestRunner()
 180     runner.run(suite)
 181