src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15 from soc.config.endian import bigendian
  16
  17 from soc.decoder.power_decoder import create_pdecode
  18 from soc.decoder.power_decoder2 import PowerDecode2
  19
  20 from soc.simple.issuer import TestIssuer
  21 from soc.experiment.compalu_multi import find_ok  # hack
  22
  23 from soc.config.test.test_loadstore import TestMemPspec
  24 from soc.simple.test.test_core import (setup_regs, check_regs,
  25                                        wait_for_busy_clear,
  26                                        wait_for_busy_hi)
  27 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  28                                                  check_sim_memory)
  29 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  30
  31 # test with ALU data and Logical data
  32 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  33 from soc.fu.div.test.test_pipe_caller import DivTestCases
  34 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  35 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  36 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  37 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  38 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  39 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  40 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  41 #from soc.simulator.test_helloworld_sim import HelloTestCases
  42
  43
  44 def setup_i_memory(imem, startaddr, instructions):
  45     mem = imem
  46     print("insn before, init mem", mem.depth, mem.width, mem,
  47           len(instructions))
  48     for i in range(mem.depth):
  49         yield mem._array[i].eq(0)
  50     yield Settle()
  51     startaddr //= 4  # instructions are 32-bit
  52     if mem.width == 32:
  53         mask = ((1 << 32)-1)
  54         for ins in instructions:
  55             if isinstance(ins, tuple):
  56                 insn, code = ins
  57             else:
  58                 insn, code = ins, ''
  59             insn = insn & 0xffffffff
  60             yield mem._array[startaddr].eq(insn)
  61             yield Settle()
  62             if insn != 0:
  63                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  64             startaddr += 1
  65             startaddr = startaddr & mask
  66         return
  67
  68     # 64 bit
  69     mask = ((1 << 64)-1)
  70     for ins in instructions:
  71         if isinstance(ins, tuple):
  72             insn, code = ins
  73         else:
  74             insn, code = ins, ''
  75         insn = insn & 0xffffffff
  76         msbs = (startaddr >> 1) & mask
  77         val = yield mem._array[msbs]
  78         if insn != 0:
  79             print("before set", hex(4*startaddr),
  80                   hex(msbs), hex(val), hex(insn))
  81         lsb = 1 if (startaddr & 1) else 0
  82         val = (val | (insn << (lsb*32)))
  83         val = val & mask
  84         yield mem._array[msbs].eq(val)
  85         yield Settle()
  86         if insn != 0:
  87             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  88             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  89         startaddr += 1
  90         startaddr = startaddr & mask
  91
  92
  93 def set_dmi(dmi, addr, data):
  94     yield dmi.req_i.eq(1)
  95     yield dmi.addr_i.eq(addr)
  96     yield dmi.din.eq(data)
  97     yield dmi.we_i.eq(1)
  98     while True:
  99         ack = yield dmi.ack_o
 100         if ack:
 101             break
 102         yield
 103     yield dmi.req_i.eq(0)
 104     yield dmi.addr_i.eq(0)
 105     yield dmi.din.eq(0)
 106     yield dmi.we_i.eq(0)
 107
 108
 109 def get_dmi(dmi, addr):
 110     yield dmi.req_i.eq(1)
 111     yield dmi.addr_i.eq(addr)
 112     yield dmi.din.eq(0)
 113     yield dmi.we_i.eq(1)
 114     while True:
 115         ack = yield dmi.ack_o
 116         if ack:
 117             break
 118         yield
 119     yield # wait one
 120     data = yield dmi.dout # get data after ack valid for 1 cycle
 121     yield dmi.req_i.eq(0)
 122     yield dmi.addr_i.eq(0)
 123     yield dmi.we_i.eq(0)
 124     return data
 125
 126
 127 class TestRunner(FHDLTestCase):
 128     def __init__(self, tst_data):
 129         super().__init__("run_all")
 130         self.test_data = tst_data
 131
 132     def run_all(self):
 133         m = Module()
 134         comb = m.d.comb
 135         pc_i = Signal(32)
 136
 137         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 138                              imem_ifacetype='test_bare_wb',
 139                              addr_wid=48,
 140                              mask_wid=8,
 141                              imem_reg_wid=64,
 142                              reg_wid=64)
 143         m.submodules.issuer = issuer = TestIssuer(pspec)
 144         imem = issuer.imem._get_memory()
 145         core = issuer.core
 146         dmi = issuer.dbg.dmi
 147         pdecode2 = issuer.pdecode2
 148         l0 = core.l0
 149
 150         # copy of the decoder for simulator
 151         simdec = create_pdecode()
 152         simdec2 = PowerDecode2(simdec)
 153         m.submodules.simdec2 = simdec2  # pain in the neck
 154
 155         comb += issuer.pc_i.data.eq(pc_i)
 156
 157         # nmigen Simulation
 158         sim = Simulator(m)
 159         sim.add_clock(1e-6)
 160
 161         def process():
 162
 163             # start in stopped
 164             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 165             yield
 166             yield
 167
 168             for test in self.test_data:
 169
 170                 # pull a reset
 171                 #yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 172
 173                 # set up bigendian (TODO: don't do this, use MSR)
 174                 yield issuer.core_bigendian_i.eq(bigendian)
 175                 yield Settle()
 176
 177                 yield
 178                 yield
 179                 yield
 180                 yield
 181
 182                 print(test.name)
 183                 program = test.program
 184                 self.subTest(test.name)
 185                 print("regs", test.regs)
 186                 print("sprs", test.sprs)
 187                 print("cr", test.cr)
 188                 print("mem", test.mem)
 189                 print("msr", test.msr)
 190                 print("assem", program.assembly)
 191                 gen = list(program.generate_instructions())
 192                 insncode = program.assembly.splitlines()
 193                 instructions = list(zip(gen, insncode))
 194                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 195                           test.msr,
 196                           initial_insns=gen, respect_pc=True,
 197                           disassembly=insncode,
 198                           bigendian=bigendian)
 199
 200                 pc = 0  # start address
 201                 counter = 0 # test to pause/start
 202
 203                 yield from setup_i_memory(imem, pc, instructions)
 204                 yield from setup_test_memory(l0, sim)
 205                 yield from setup_regs(pdecode2, core, test)
 206
 207                 yield pc_i.eq(pc)
 208                 yield issuer.pc_i.ok.eq(1)
 209                 yield
 210
 211                 print("instructions", instructions)
 212
 213                 index = sim.pc.CIA.value//4
 214                 while index < len(instructions):
 215                     ins, code = instructions[index]
 216
 217                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 218                     print(index, code)
 219
 220                     if counter == 0:
 221                         # start the core
 222                         yield
 223                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
 224                         yield issuer.pc_i.ok.eq(0)  # no change PC after this
 225                         yield
 226                         yield
 227
 228                     counter = counter + 1
 229
 230                     # wait until executed
 231                     yield from wait_for_busy_hi(core)
 232                     yield from wait_for_busy_clear(core)
 233
 234                     # set up simulated instruction (in simdec2)
 235                     try:
 236                         yield from sim.setup_one()
 237                     except KeyError:  # indicates instruction not in imem: stop
 238                         break
 239                     yield Settle()
 240
 241                     # call simulated operation
 242                     print("sim", code)
 243                     yield from sim.execute_one()
 244                     yield Settle()
 245                     index = sim.pc.CIA.value//4
 246
 247                     terminated = yield issuer.dbg.terminated_o
 248                     print("terminated", terminated)
 249
 250                     # register check
 251                     yield from check_regs(self, sim, core, test, code)
 252
 253                     # Memory check
 254                     yield from check_sim_memory(self, l0, sim, code)
 255
 256                     terminated = yield issuer.dbg.terminated_o
 257                     if terminated:
 258                         break
 259
 260                 # test of dmi reg get
 261                 int_reg = 9
 262                 yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg) # int reg 9
 263                 value = yield from get_dmi(dmi, DBGCore.GSPR_DATA) # get data
 264
 265                 print ("after test %s reg %x value %s" % \
 266                             (test.name, int_reg, value))
 267
 268         sim.add_sync_process(process)
 269         with sim.write_vcd("issuer_simulator.vcd",
 270                            traces=[]):
 271             sim.run()
 272
 273
 274 if __name__ == "__main__":
 275     unittest.main(exit=False)
 276     suite = unittest.TestSuite()
 277     # suite.addTest(TestRunner(HelloTestCases.test_data))
 278     suite.addTest(TestRunner(DivTestCases().test_data))
 279     # suite.addTest(TestRunner(AttnTestCase.test_data))
 280     suite.addTest(TestRunner(GeneralTestCases.test_data))
 281     # suite.addTest(TestRunner(LDSTTestCase().test_data))
 282     # suite.addTest(TestRunner(CRTestCase().test_data))
 283     # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 284     suite.addTest(TestRunner(LogicalTestCase().test_data))
 285     suite.addTest(TestRunner(ALUTestCase().test_data))
 286     # suite.addTest(TestRunner(BranchTestCase.test_data))
 287     # suite.addTest(TestRunner(SPRTestCase.test_data))
 288
 289     runner = unittest.TextTestRunner()
 290     runner.run(suite)