1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
27 # test with ALU data and Logical data
28 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
29 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
30 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
31 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
32 from soc
.fu
.branch
.test
.test_pipe_caller
import BranchTestCase
33 from soc
.fu
.spr
.test
.test_pipe_caller
import SPRTestCase
34 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
35 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
38 def setup_i_memory(imem
, startaddr
, instructions
):
40 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
,
42 for i
in range(mem
.depth
):
43 yield mem
._array
[i
].eq(0)
45 startaddr
//= 4 # instructions are 32-bit
47 for ins
in instructions
:
48 if isinstance(ins
, tuple):
52 msbs
= (startaddr
>>1) & mask
53 val
= yield mem
._array
[msbs
]
55 print ("before set", hex(4*startaddr
),
56 hex(msbs
), hex(val
), hex(insn
))
57 lsb
= 1 if (startaddr
& 1) else 0
58 val
= (val |
(insn
<< (lsb
*32))) & mask
59 yield mem
._array
[msbs
].eq(val
)
62 print ("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
63 print ("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
65 startaddr
= startaddr
& mask
68 class TestRunner(FHDLTestCase
):
69 def __init__(self
, tst_data
):
70 super().__init
__("run_all")
71 self
.test_data
= tst_data
79 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
80 imem_ifacetype
='test_bare_wb',
84 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
85 imem
= issuer
.imem
._get
_memory
()
87 pdecode2
= core
.pdecode2
90 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
91 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
99 for test
in self
.test_data
:
102 yield core
.core_start_i
.eq(1)
104 yield core
.core_start_i
.eq(0)
108 program
= test
.program
109 self
.subTest(test
.name
)
110 print ("regs", test
.regs
)
111 print ("sprs", test
.sprs
)
112 print ("cr", test
.cr
)
113 print ("mem", test
.mem
)
114 print ("msr", test
.msr
)
115 print ("assem", program
.assembly
)
116 gen
= list(program
.generate_instructions())
117 insncode
= program
.assembly
.splitlines()
118 instructions
= list(zip(gen
, insncode
))
119 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
121 initial_insns
=gen
, respect_pc
=True,
122 disassembly
=insncode
)
124 pc
= 0 # start address
126 yield from setup_i_memory(imem
, pc
, instructions
)
127 yield from setup_test_memory(l0
, sim
)
128 yield from setup_regs(core
, test
)
131 yield issuer
.pc_i
.ok
.eq(1)
133 index
= sim
.pc
.CIA
.value
//4
134 while index
< len(instructions
):
135 ins
, code
= instructions
[index
]
137 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
140 # start the instruction
141 yield go_insn_i
.eq(1)
143 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
144 yield go_insn_i
.eq(0) # and don't issue a new insn
147 # wait until executed
148 #yield from wait_for_busy_hi(core)
150 yield from wait_for_busy_clear(core
)
152 terminated
= yield core
.core_terminated_o
153 print ("terminated", terminated
)
156 # call simulated operation
157 opname
= code
.split(' ')[0]
158 yield from sim
.call(opname
)
160 index
= sim
.pc
.CIA
.value
//4
163 yield from check_regs(self
, sim
, core
, test
, code
)
166 yield from check_sim_memory(self
, l0
, sim
, code
)
168 terminated
= yield core
.core_terminated_o
172 sim
.add_sync_process(process
)
173 with sim
.write_vcd("issuer_simulator.vcd",
178 if __name__
== "__main__":
179 unittest
.main(exit
=False)
180 suite
= unittest
.TestSuite()
181 suite
.addTest(TestRunner(AttnTestCase
.test_data
))
182 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
183 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
184 suite
.addTest(TestRunner(CRTestCase
.test_data
))
185 suite
.addTest(TestRunner(ShiftRotTestCase
.test_data
))
186 suite
.addTest(TestRunner(LogicalTestCase
.test_data
))
187 suite
.addTest(TestRunner(ALUTestCase
.test_data
))
188 suite
.addTest(TestRunner(BranchTestCase
.test_data
))
189 suite
.addTest(TestRunner(SPRTestCase
.test_data
))
191 runner
= unittest
.TextTestRunner()