src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15 from soc.config.endian import bigendian
  16
  17 from soc.simple.issuer import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok # hack
  19
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.simple.test.test_core import (setup_regs, check_regs,
  22                                        wait_for_busy_clear,
  23                                        wait_for_busy_hi)
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26
  27 # test with ALU data and Logical data
  28 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  29 #from soc.fu.div.test.test_pipe_caller import DivTestCase
  30 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  31 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  32 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
  33 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  34 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  35 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  36 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  37 #from soc.simulator.test_helloworld_sim import HelloTestCases
  38
  39
  40 def setup_i_memory(imem, startaddr, instructions):
  41     mem = imem
  42     print ("insn before, init mem", mem.depth, mem.width, mem,
  43                                     len(instructions))
  44     for i in range(mem.depth):
  45         yield mem._array[i].eq(0)
  46     yield Settle()
  47     startaddr //= 4 # instructions are 32-bit
  48     mask = ((1<<64)-1)
  49     for ins in instructions:
  50         if isinstance(ins, tuple):
  51             insn, code = ins
  52         else:
  53             insn, code = ins, ''
  54         insn = insn & 0xffffffff
  55         msbs = (startaddr>>1) & mask
  56         val = yield mem._array[msbs]
  57         if insn != 0:
  58             print ("before set", hex(4*startaddr),
  59                                  hex(msbs), hex(val), hex(insn))
  60         lsb = 1 if (startaddr & 1) else 0
  61         val = (val | (insn << (lsb*32)))
  62         val = val & mask
  63         yield mem._array[msbs].eq(val)
  64         yield Settle()
  65         if insn != 0:
  66             print ("after  set", hex(4*startaddr), hex(msbs), hex(val))
  67             print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  68         startaddr += 1
  69         startaddr = startaddr & mask
  70
  71
  72 class TestRunner(FHDLTestCase):
  73     def __init__(self, tst_data):
  74         super().__init__("run_all")
  75         self.test_data = tst_data
  76
  77     def run_all(self):
  78         m = Module()
  79         comb = m.d.comb
  80         go_insn_i = Signal()
  81         pc_i = Signal(32)
  82
  83         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  84                              imem_ifacetype='test_bare_wb',
  85                              addr_wid=48,
  86                              mask_wid=8,
  87                              reg_wid=64)
  88         m.submodules.issuer = issuer = TestIssuer(pspec)
  89         imem = issuer.imem._get_memory()
  90         core = issuer.core
  91         pdecode2 = core.pdecode2
  92         l0 = core.l0
  93
  94         comb += issuer.pc_i.data.eq(pc_i)
  95         comb += issuer.go_insn_i.eq(go_insn_i)
  96
  97         # nmigen Simulation
  98         sim = Simulator(m)
  99         sim.add_clock(1e-6)
 100
 101         def process():
 102
 103             for test in self.test_data:
 104
 105                 # get core going
 106                 yield core.bigendian_i.eq(bigendian)
 107                 yield core.core_start_i.eq(1)
 108                 yield
 109                 yield core.core_start_i.eq(0)
 110                 yield Settle()
 111
 112                 print(test.name)
 113                 program = test.program
 114                 self.subTest(test.name)
 115                 print ("regs", test.regs)
 116                 print ("sprs", test.sprs)
 117                 print ("cr", test.cr)
 118                 print ("mem", test.mem)
 119                 print ("msr", test.msr)
 120                 print ("assem", program.assembly)
 121                 gen = list(program.generate_instructions())
 122                 insncode = program.assembly.splitlines()
 123                 instructions = list(zip(gen, insncode))
 124                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 125                           test.msr,
 126                           initial_insns=gen, respect_pc=True,
 127                           disassembly=insncode,
 128                           bigendian=bigendian)
 129
 130                 pc = 0 # start address
 131
 132                 yield from setup_i_memory(imem, pc, instructions)
 133                 yield from setup_test_memory(l0, sim)
 134                 yield from setup_regs(core, test)
 135
 136                 yield pc_i.eq(pc)
 137                 yield issuer.pc_i.ok.eq(1)
 138
 139                 index = sim.pc.CIA.value//4
 140                 while index < len(instructions):
 141                     ins, code = instructions[index]
 142
 143                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 144                     print(index, code)
 145
 146                     # start the instruction
 147                     yield go_insn_i.eq(1)
 148                     yield
 149                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 150                     yield go_insn_i.eq(0)      # and don't issue a new insn
 151                     yield Settle()
 152
 153                     # wait until executed
 154                     yield from wait_for_busy_hi(core)
 155                     yield from wait_for_busy_clear(core)
 156
 157                     terminated = yield core.core_terminated_o
 158                     print ("terminated", terminated)
 159
 160                     print ("sim", code)
 161                     # call simulated operation
 162                     opname = code.split(' ')[0]
 163                     yield from sim.call(opname)
 164                     yield Settle()
 165                     index = sim.pc.CIA.value//4
 166
 167                     # register check
 168                     yield from check_regs(self, sim, core, test, code)
 169
 170                     # Memory check
 171                     yield from check_sim_memory(self, l0, sim, code)
 172
 173                     terminated = yield core.core_terminated_o
 174                     if terminated:
 175                         break
 176
 177         sim.add_sync_process(process)
 178         with sim.write_vcd("issuer_simulator.vcd",
 179                             traces=[]):
 180             sim.run()
 181
 182
 183 if __name__ == "__main__":
 184     unittest.main(exit=False)
 185     suite = unittest.TestSuite()
 186     #suite.addTest(TestRunner(HelloTestCases.test_data))
 187     #suite.addTest(TestRunner(DivTestCase.test_data))
 188     suite.addTest(TestRunner(AttnTestCase.test_data))
 189     suite.addTest(TestRunner(GeneralTestCases.test_data))
 190     suite.addTest(TestRunner(LDSTTestCase.test_data))
 191     #suite.addTest(TestRunner(CRTestCase.test_data))
 192     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 193     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 194     #suite.addTest(TestRunner(ALUTestCase.test_data))
 195     #suite.addTest(TestRunner(BranchTestCase.test_data))
 196     #suite.addTest(TestRunner(SPRTestCase.test_data))
 197
 198     runner = unittest.TextTestRunner()
 199     runner.run(suite)
 200