src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15
  16
  17 from soc.simple.issuer import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok # hack
  19
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.simple.test.test_core import (setup_regs, check_regs,
  22                                        wait_for_busy_clear,
  23                                        wait_for_busy_hi)
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26
  27 # test with ALU data and Logical data
  28 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  29 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  30 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  31 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  32 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  33 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  34 from soc.simulator.test_sim import GeneralTestCases
  35
  36
  37 def setup_i_memory(imem, startaddr, instructions):
  38     mem = imem
  39     print ("insn before, init mem", mem.depth, mem.width, mem)
  40     for i in range(mem.depth):
  41         yield mem._array[i].eq(0)
  42     yield Settle()
  43     startaddr //= 4 # instructions are 32-bit
  44     mask = ((1<<64)-1)
  45     for insn, code in instructions:
  46         msbs = (startaddr>>1) & mask
  47         val = yield mem._array[msbs]
  48         print ("before set", hex(startaddr), hex(msbs), hex(val))
  49         lsb = 1 if (startaddr & 1) else 0
  50         val = (val | (insn << (lsb*32))) & mask
  51         yield mem._array[msbs].eq(val)
  52         yield Settle()
  53         print ("after  set", hex(startaddr), hex(msbs), hex(val))
  54         print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  55         startaddr += 1
  56         startaddr = startaddr & mask
  57
  58
  59 class TestRunner(FHDLTestCase):
  60     def __init__(self, tst_data):
  61         super().__init__("run_all")
  62         self.test_data = tst_data
  63
  64     def run_all(self):
  65         m = Module()
  66         comb = m.d.comb
  67         go_insn_i = Signal()
  68         pc_i = Signal(32)
  69
  70         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  71                              imem_ifacetype='test_bare_wb',
  72                              addr_wid=48,
  73                              mask_wid=8,
  74                              reg_wid=64)
  75         m.submodules.issuer = issuer = TestIssuer(pspec)
  76         imem = issuer.imem._get_memory()
  77         core = issuer.core
  78         pdecode2 = core.pdecode2
  79         l0 = core.l0
  80
  81         comb += issuer.pc_i.data.eq(pc_i)
  82         comb += issuer.go_insn_i.eq(go_insn_i)
  83
  84         # nmigen Simulation
  85         sim = Simulator(m)
  86         sim.add_clock(1e-6)
  87
  88         def process():
  89
  90             for test in self.test_data:
  91                 print(test.name)
  92                 program = test.program
  93                 self.subTest(test.name)
  94                 print ("regs", test.regs)
  95                 print ("sprs", test.sprs)
  96                 print ("cr", test.cr)
  97                 print ("mem", test.mem)
  98                 print ("msr", test.msr)
  99                 print ("assem", program.assembly)
 100                 gen = list(program.generate_instructions())
 101                 insncode = program.assembly.splitlines()
 102                 instructions = list(zip(gen, insncode))
 103                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 104                           test.msr,
 105                           initial_insns=gen, respect_pc=True,
 106                           disassembly=insncode)
 107
 108                 pc = 0 # start address
 109
 110                 yield from setup_i_memory(imem, pc, instructions)
 111                 yield from setup_test_memory(l0, sim)
 112                 yield from setup_regs(core, test)
 113
 114                 yield pc_i.eq(pc)
 115                 yield issuer.pc_i.ok.eq(1)
 116
 117                 index = sim.pc.CIA.value//4
 118                 while index < len(instructions):
 119                     ins, code = instructions[index]
 120
 121                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 122                     print(index, code)
 123
 124                     # start the instruction
 125                     yield go_insn_i.eq(1)
 126                     yield
 127                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 128                     yield go_insn_i.eq(0)      # and don't issue a new insn
 129
 130                     # wait until executed
 131                     yield from wait_for_busy_hi(core)
 132                     yield from wait_for_busy_clear(core)
 133
 134                     print ("sim", code)
 135                     # call simulated operation
 136                     opname = code.split(' ')[0]
 137                     yield from sim.call(opname)
 138                     yield Settle()
 139                     index = sim.pc.CIA.value//4
 140
 141                     # register check
 142                     yield from check_regs(self, sim, core, test, code)
 143
 144                     # Memory check
 145                     yield from check_sim_memory(self, l0, sim, code)
 146
 147         sim.add_sync_process(process)
 148         with sim.write_vcd("issuer_simulator.vcd",
 149                             traces=[]):
 150             sim.run()
 151
 152
 153 if __name__ == "__main__":
 154     unittest.main(exit=False)
 155     suite = unittest.TestSuite()
 156     suite.addTest(TestRunner(GeneralTestCases.test_data))
 157     suite.addTest(TestRunner(LDSTTestCase.test_data))
 158     suite.addTest(TestRunner(CRTestCase.test_data))
 159     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 160     suite.addTest(TestRunner(LogicalTestCase.test_data))
 161     suite.addTest(TestRunner(ALUTestCase.test_data))
 162     suite.addTest(TestRunner(BranchTestCase.test_data))
 163
 164     runner = unittest.TextTestRunner()
 165     runner.run(suite)
 166