1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
15 from soc
.config
.endian
import bigendian
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
27 # test with ALU data and Logical data
28 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
29 #from soc.fu.div.test.test_pipe_caller import DivTestCase
30 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
31 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
32 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
33 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
34 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
35 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
36 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
37 #from soc.simulator.test_helloworld_sim import HelloTestCases
40 def setup_i_memory(imem
, startaddr
, instructions
):
42 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
44 for i
in range(mem
.depth
):
45 yield mem
._array
[i
].eq(0)
47 startaddr
//= 4 # instructions are 32-bit
50 for ins
in instructions
:
51 if isinstance(ins
, tuple):
55 insn
= insn
& 0xffffffff
56 yield mem
._array
[startaddr
].eq(insn
)
59 print ("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
61 startaddr
= startaddr
& mask
66 for ins
in instructions
:
67 if isinstance(ins
, tuple):
71 insn
= insn
& 0xffffffff
72 msbs
= (startaddr
>> 1) & mask
73 val
= yield mem
._array
[msbs
]
75 print("before set", hex(4*startaddr
),
76 hex(msbs
), hex(val
), hex(insn
))
77 lsb
= 1 if (startaddr
& 1) else 0
78 val
= (val |
(insn
<< (lsb
*32)))
80 yield mem
._array
[msbs
].eq(val
)
83 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
84 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
86 startaddr
= startaddr
& mask
89 class TestRunner(FHDLTestCase
):
90 def __init__(self
, tst_data
):
91 super().__init
__("run_all")
92 self
.test_data
= tst_data
100 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
101 imem_ifacetype
='test_bare_wb',
106 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
107 imem
= issuer
.imem
._get
_memory
()
109 pdecode2
= core
.pdecode2
112 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
113 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
121 for test
in self
.test_data
:
124 yield issuer
.core_bigendian_i
.eq(bigendian
)
125 yield issuer
.core_start_i
.eq(1)
127 yield issuer
.core_start_i
.eq(0)
131 program
= test
.program
132 self
.subTest(test
.name
)
133 print("regs", test
.regs
)
134 print("sprs", test
.sprs
)
136 print("mem", test
.mem
)
137 print("msr", test
.msr
)
138 print("assem", program
.assembly
)
139 gen
= list(program
.generate_instructions())
140 insncode
= program
.assembly
.splitlines()
141 instructions
= list(zip(gen
, insncode
))
142 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
144 initial_insns
=gen
, respect_pc
=True,
145 disassembly
=insncode
,
148 pc
= 0 # start address
150 yield from setup_i_memory(imem
, pc
, instructions
)
151 yield from setup_test_memory(l0
, sim
)
152 yield from setup_regs(core
, test
)
155 yield issuer
.pc_i
.ok
.eq(1)
157 index
= sim
.pc
.CIA
.value
//4
158 while index
< len(instructions
):
159 ins
, code
= instructions
[index
]
161 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
164 # start the instruction
165 yield go_insn_i
.eq(1)
167 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
168 yield go_insn_i
.eq(0) # and don't issue a new insn
171 # wait until executed
172 yield from wait_for_busy_hi(core
)
173 yield from wait_for_busy_clear(core
)
175 terminated
= yield issuer
.halted_o
176 print("terminated", terminated
)
179 # call simulated operation
180 opname
= code
.split(' ')[0]
181 yield from sim
.call(opname
)
183 index
= sim
.pc
.CIA
.value
//4
186 yield from check_regs(self
, sim
, core
, test
, code
)
189 yield from check_sim_memory(self
, l0
, sim
, code
)
191 terminated
= yield issuer
.halted_o
195 sim
.add_sync_process(process
)
196 with sim
.write_vcd("issuer_simulator.vcd",
201 if __name__
== "__main__":
202 unittest
.main(exit
=False)
203 suite
= unittest
.TestSuite()
204 # suite.addTest(TestRunner(HelloTestCases.test_data))
205 # suite.addTest(TestRunner(DivTestCase.test_data))
206 suite
.addTest(TestRunner(AttnTestCase
.test_data
))
207 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
208 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
209 # suite.addTest(TestRunner(CRTestCase.test_data))
210 # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
211 # suite.addTest(TestRunner(LogicalTestCase.test_data))
212 # suite.addTest(TestRunner(ALUTestCase.test_data))
213 # suite.addTest(TestRunner(BranchTestCase.test_data))
214 # suite.addTest(TestRunner(SPRTestCase.test_data))
216 runner
= unittest
.TextTestRunner()