src/soc/simple/test/test_issuer_dcache.py

   1 """dcbz test case
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=51
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 ##########
  22 from openpower.simulator.program import Program
  23 from openpower.endian import bigendian
  24 from openpower.test.common import TestAccumulatorBase
  25
  26 class DCBZTestCase(TestAccumulatorBase):
  27
  28     def case_1_dcbz(self):
  29         lst = ["dcbz 1, 2"]
  30         initial_regs = [0] * 32
  31         initial_regs[1] = 0x0004
  32         initial_regs[2] = 0x0008
  33         initial_mem = {0x0000: (0x5432123412345678, 8),
  34                        0x0008: (0xabcdef0187654321, 8),
  35                        0x0020: (0x1828384822324252, 8),
  36                         }
  37         self.add_case(Program(lst, bigendian), initial_regs,
  38                              initial_mem=initial_mem)
  39 ##########
  40
  41
  42 if __name__ == "__main__":
  43     svp64 = False
  44
  45     unittest.main(exit=False)
  46     suite = unittest.TestSuite()
  47
  48     # add other test cases later
  49     suite.addTest(TestRunner(DCBZTestCase().test_data, svp64=svp64,
  50                               microwatt_mmu=True))
  51
  52     runner = unittest.TextTestRunner()
  53     runner.run(suite)