sort out misaligned store in LoadStore1
[soc.git] / src / soc / simple / test / test_issuer_dcache.py
1 """simple core test, runs instructions from a TestMemory
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 import sys
13
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc.simple.test.test_runner import TestRunner
20
21 # test dcbz with MMU an DCACHE
22 #from openpower.test.mmu.mmu_cases import MMUTestCase
23 #from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
24 #from openpower.test.ldst.ldst_cases import LDSTTestCase
25 #from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
26 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
27
28 ##########
29 from openpower.simulator.program import Program
30 from openpower.endian import bigendian
31 from openpower.test.common import TestAccumulatorBase
32
33
34 #TODO run this test case later
35 class DCBZTestCase(TestAccumulatorBase):
36
37 def case_1_dcbz(self):
38 lst = ["dcbz 1, 2"]
39 initial_regs = [0] * 32
40 initial_regs[1] = 0x0004
41 initial_regs[2] = 0x0008
42 initial_mem = {0x0000: (0x5432123412345678, 8),
43 0x0008: (0xabcdef0187654321, 8),
44 0x0020: (0x1828384822324252, 8),
45 }
46 self.add_case(Program(lst, bigendian), initial_regs,
47 initial_mem=initial_mem)
48 ##########
49
50
51 if __name__ == "__main__":
52 svp64 = False
53 #if len(sys.argv) == 2:
54 # if sys.argv[1] == 'nosvp64':
55 # svp64 = False
56 # sys.argv.pop()
57 #print ("SVP64 test mode enabled", svp64)
58
59 unittest.main(exit=False)
60 suite = unittest.TestSuite()
61 #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64,
62 # microwatt_mmu=True))
63 #suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
64 # microwatt_mmu=True))
65
66 # without ROM set
67 #suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
68 # microwatt_mmu=True))
69
70 # TODO: write DCBZ test case
71 suite.addTest(TestRunner(DCBZTestCase().test_data, svp64=svp64,
72 microwatt_mmu=True))
73
74 # LD/ST exception cases
75 #suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
76 # microwatt_mmu=True))
77
78 runner = unittest.TextTestRunner()
79 runner.run(suite)