in LoadStore1 capture the address for misaligned dual ld/sts in
[soc.git] / src / soc / simple / test / test_issuer_mmu.py
1 """simple core test, runs instructions from a TestMemory
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 import sys
13
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc.simple.test.test_runner import TestRunner
20
21 # test with MMU
22 from openpower.test.mmu.mmu_cases import MMUTestCase
23 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
24 from openpower.test.ldst.ldst_cases import LDSTTestCase
25 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
26 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
27
28 if __name__ == "__main__":
29 svp64 = True
30 if len(sys.argv) == 2:
31 if sys.argv[1] == 'nosvp64':
32 svp64 = False
33 sys.argv.pop()
34
35 print ("SVP64 test mode enabled", svp64)
36
37 unittest.main(exit=False)
38 suite = unittest.TestSuite()
39 #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64,
40 # microwatt_mmu=True))
41 #suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
42 # microwatt_mmu=True))
43
44 # without ROM set
45 #suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
46 # microwatt_mmu=True))
47
48 # LD/ST tests should all still work
49 suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
50 microwatt_mmu=True))
51
52 # LD/ST exception cases
53 suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
54 microwatt_mmu=True))
55
56 runner = unittest.TextTestRunner()
57 runner.run(suite)