1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc
.simple
.test
.test_runner
import TestRunner
22 from openpower
.test
.mmu
.mmu_cases
import MMUTestCase
23 #from openpower.test.ldst.ldst_cases import LDSTTestCase
24 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
26 if __name__
== "__main__":
28 if len(sys
.argv
) == 2:
29 if sys
.argv
[1] == 'nosvp64':
33 print ("SVP64 test mode enabled", svp64
)
35 unittest
.main(exit
=False)
36 suite
= unittest
.TestSuite()
37 #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64,
38 # microwatt_mmu=True))
39 #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
40 # microwatt_mmu=True))
41 suite
.addTest(TestRunner(MMUTestCase().test_data
, svp64
=svp64
,
44 runner
= unittest
.TextTestRunner()