1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc
.simple
.test
.test_runner
import TestRunner
22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
25 from openpower
.test
.mmu
.mmu_cases
import MMUTestCase
26 from openpower
.test
.mmu
.mmu_rom_cases
import MMUTestCaseROM
, default_mem
27 from openpower
.test
.ldst
.ldst_cases
import LDSTTestCase
28 from openpower
.test
.ldst
.ldst_exc_cases
import LDSTExceptionTestCase
29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
31 from openpower
.simulator
.program
import Program
32 from openpower
.endian
import bigendian
33 from openpower
.test
.common
import TestAccumulatorBase
35 class MMUTestCase(TestAccumulatorBase
):
37 # now working correctly
38 def case_1_dcbz(self
):
39 lst
= ["dcbz 1, 2", # MMUTEST.DCBZ: EA from adder 12
40 "dcbz 1, 3"] # MMUTEST.DCBZ: EA from adder 11
41 initial_regs
= [0] * 32
42 initial_regs
[1] = 0x0004
43 initial_regs
[2] = 0x0008
44 initial_regs
[3] = 0x0007
46 self
.add_case(Program(lst
, bigendian
), initial_regs
,
47 initial_mem
=initial_mem
)
49 # MMUTEST: OP_TLBIE: insn_bits=39
50 def case_2_tlbie(self
):
51 lst
= ["tlbie 1,1,1,1,1"] # tlbie RB,RS,RIC,PRS,R
52 initial_regs
= [0] * 32
54 self
.add_case(Program(lst
, bigendian
), initial_regs
,
55 initial_mem
=initial_mem
)
58 def case_3_mtspr(self
):
59 lst
= ["mtspr 720,1"] # mtspr PRTBL,r1
60 initial_regs
= [0] * 32
61 initial_regs
[1] = 0x1234
63 self
.add_case(Program(lst
, bigendian
), initial_regs
,
64 initial_mem
=initial_mem
)
67 def case_4_mfspr(self
):
68 lst
= ["mfspr 1,18", # mtspr r1,DSISR
69 "mfspr 2,19"] # mtspr r2,DAR
70 initial_regs
= [0] * 32
71 initial_regs
[1] = 0x1234
72 initial_regs
[2] = 0x3456
74 self
.add_case(Program(lst
, bigendian
), initial_regs
,
75 initial_mem
=initial_mem
)
77 if __name__
== "__main__":
79 if len(sys
.argv
) == 2:
80 if sys
.argv
[1] == 'nosvp64':
84 print ("SVP64 test mode enabled", svp64
)
86 unittest
.main(exit
=False)
87 suite
= unittest
.TestSuite()
89 # MMU/DCache integration tests
90 suite
.addTest(TestRunner(MMUTestCase().test_data
, svp64
=svp64
,
93 runner
= unittest
.TextTestRunner()