1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc
.simple
.test
.test_runner
import TestRunner
22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
25 from openpower
.test
.mmu
.mmu_cases
import MMUTestCase
26 from openpower
.test
.mmu
.mmu_rom_cases
import MMUTestCaseROM
, default_mem
27 from openpower
.test
.ldst
.ldst_cases
import LDSTTestCase
28 from openpower
.test
.ldst
.ldst_exc_cases
import LDSTExceptionTestCase
29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
31 from openpower
.simulator
.program
import Program
32 from openpower
.endian
import bigendian
33 from openpower
.test
.common
import TestAccumulatorBase
35 from openpower
.consts
import MSR
37 class MMUTestCase(TestAccumulatorBase
):
39 # now working correctly
40 def case_1_dcbz(self
):
41 lst
= ["dcbz 1, 2", # MMUTEST.DCBZ: EA from adder 12
42 "dcbz 1, 3"] # MMUTEST.DCBZ: EA from adder 11
43 initial_regs
= [0] * 32
44 initial_regs
[1] = 0x0004
45 initial_regs
[2] = 0x0008
46 initial_regs
[3] = 0x0007
48 self
.add_case(Program(lst
, bigendian
), initial_regs
,
49 initial_mem
=initial_mem
)
51 # MMUTEST: OP_TLBIE: insn_bits=39
52 def case_2_tlbie(self
):
53 lst
= ["tlbie 1,1,1,1,1"] # tlbie RB,RS,RIC,PRS,R
54 initial_regs
= [0] * 32
56 self
.add_case(Program(lst
, bigendian
), initial_regs
,
57 initial_mem
=initial_mem
)
60 def case_3_mtspr(self
):
61 lst
= ["mtspr 720,1"] # mtspr PRTBL,r1
62 initial_regs
= [0] * 32
63 initial_regs
[1] = 0x1234
65 self
.add_case(Program(lst
, bigendian
), initial_regs
,
66 initial_mem
=initial_mem
)
69 def case_4_mfspr(self
):
70 lst
= ["mfspr 1,18", # mtspr r1,DSISR
71 "mfspr 2,19"] # mtspr r2,DAR
72 initial_regs
= [0] * 32
73 initial_regs
[1] = 0x1234
74 initial_regs
[2] = 0x3456
76 self
.add_case(Program(lst
, bigendian
), initial_regs
,
77 initial_mem
=initial_mem
)
79 # new testcase for all sprs
80 def case_5_allsprs(self
):
81 lst
= ["mtspr 720,1", #MMUTEST: OP_MTSPR: spr=720
82 "mtspr 48,2", #MMUTEST: OP_MTSPR: spr=48
83 "mtspr 18,3", #MMUTEST: OP_MTSPR: spr=18
84 "mtspr 19,4", #MMUTEST: OP_MTSPR: spr=19
85 "mfspr 5,720", #MMUTEST: OP_MFSPR: spr=720 returns=4660
86 "mfspr 6,48", #MMUTEST: OP_MFSPR: spr=48 returns=13398
87 "mfspr 7,18", #MMUTEST: OP_MFSPR: spr=18 returns=17185
88 "mfspr 8,19" #MMUTEST: OP_MFSPR: spr=19 returns=25923
90 initial_regs
= [0] * 32
91 initial_regs
[1] = 0x1234
92 initial_regs
[2] = 0x3456
93 initial_regs
[3] = 0x4321
94 initial_regs
[4] = 0x6543
96 self
.add_case(Program(lst
, bigendian
), initial_regs
,
97 initial_mem
=initial_mem
)
99 # MMUTEST: initial_msr= 16384
101 # ISACaller initial_msr 16384
102 # FIXME msr does not get passed to LoadStore1
103 def case_5_ldst_exception(self
):
104 lst
= ["stb 10,0(2)"]
105 initial_regs
= [0] * 32
106 initial_regs
[1] = 0x1234
107 initial_regs
[2] = 0x3456
108 initial_regs
[3] = 0x4321
109 initial_regs
[4] = 0x6543
110 initial_regs
[10] = 0xfe
113 initial_msr
= 1 << MSR
.PR
# must set "problem" state for virtual memory
114 print("MMUTEST: initial_msr=",initial_msr
)
115 self
.add_case(Program(lst
, bigendian
), initial_regs
,
116 initial_mem
=initial_mem
,initial_msr
=initial_msr
)
118 if __name__
== "__main__":
120 if len(sys
.argv
) == 2:
121 if sys
.argv
[1] == 'nosvp64':
125 print ("SVP64 test mode enabled", svp64
)
127 unittest
.main(exit
=False)
128 suite
= unittest
.TestSuite()
130 # MMU/DCache integration tests
131 suite
.addTest(TestRunner(MMUTestCase().test_data
, svp64
=svp64
,
134 runner
= unittest
.TextTestRunner()