src/soc/simple/test/test_issuer_mmu.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 #@platen:bookmarks
  22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
  23
  24 # test with MMU
  25 from openpower.test.mmu.mmu_cases import MMUTestCase
  26 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  27 from openpower.test.ldst.ldst_cases import LDSTTestCase
  28 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  30
  31 from openpower.simulator.program import Program
  32 from openpower.endian import bigendian
  33 from openpower.test.common import TestAccumulatorBase
  34
  35 class MMUTestCase(TestAccumulatorBase):
  36
  37     # now working correctly
  38     def case_1_dcbz(self):
  39         lst = ["dcbz 1, 2",  # MMUTEST.DCBZ: EA from adder 12
  40                "dcbz 1, 3"]  # MMUTEST.DCBZ: EA from adder 11
  41         initial_regs = [0] * 32
  42         initial_regs[1] = 0x0004
  43         initial_regs[2] = 0x0008
  44         initial_regs[3] = 0x0007
  45         initial_mem = {}
  46         self.add_case(Program(lst, bigendian), initial_regs,
  47                              initial_mem=initial_mem)
  48
  49     # MMUTEST: OP_TLBIE: insn_bits=39
  50     def case_2_tlbie(self):
  51         lst = ["tlbie 1,1,1,1,1"] # tlbie   RB,RS,RIC,PRS,R
  52         initial_regs = [0] * 32
  53         initial_mem = {}
  54         self.add_case(Program(lst, bigendian), initial_regs,
  55                              initial_mem=initial_mem)
  56
  57     # OP_MTSPR: spr=720
  58     def case_3_mtspr(self):
  59         lst = ["mtspr 720,1"] # mtspr PRTBL,r1
  60         initial_regs = [0] * 32
  61         initial_regs[1] = 0x1234
  62         initial_mem = {}
  63         self.add_case(Program(lst, bigendian), initial_regs,
  64                              initial_mem=initial_mem)
  65
  66     # OP_MFSPR: spr=18/19
  67     def case_4_mfspr(self):
  68         lst = ["mfspr 1,18", # mtspr r1,DSISR
  69                "mfspr 2,19"] # mtspr r2,DAR
  70         initial_regs = [0] * 32
  71         initial_regs[1] = 0x1234
  72         initial_regs[2] = 0x3456
  73         initial_mem = {}
  74         self.add_case(Program(lst, bigendian), initial_regs,
  75                              initial_mem=initial_mem)
  76
  77     # new testcase for all sprs
  78     def case_5_allsprs(self):
  79         lst =  ["mtspr 720,1",   #MMUTEST: OP_MTSPR: spr=720
  80                 "mtspr 48,2",    #MMUTEST: OP_MTSPR: spr=48
  81                 "mtspr 18,3",    #MMUTEST: OP_MTSPR: spr=18
  82                 "mtspr 19,4",    #MMUTEST: OP_MTSPR: spr=19
  83                 "mfspr 5,720",   #MMUTEST: OP_MFSPR: spr=720 returns=4660
  84                 "mfspr 6,48",    #MMUTEST: OP_MFSPR: spr=48 returns=13398
  85                 "mfspr 7,18",    #MMUTEST: OP_MFSPR: spr=18 returns=17185
  86                 "mfspr 8,19"     #MMUTEST: OP_MFSPR: spr=19 returns=25923
  87                 ]
  88         initial_regs = [0] * 32
  89         initial_regs[1] = 0x1234
  90         initial_regs[2] = 0x3456
  91         initial_regs[3] = 0x4321
  92         initial_regs[4] = 0x6543
  93         initial_mem = {}
  94         self.add_case(Program(lst, bigendian), initial_regs,
  95                              initial_mem=initial_mem)
  96
  97 if __name__ == "__main__":
  98     svp64 = True
  99     if len(sys.argv) == 2:
 100         if sys.argv[1] == 'nosvp64':
 101             svp64 = False
 102         sys.argv.pop()
 103
 104     print ("SVP64 test mode enabled", svp64)
 105
 106     unittest.main(exit=False)
 107     suite = unittest.TestSuite()
 108
 109     # MMU/DCache integration tests
 110     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
 111                               microwatt_mmu=True))
 112
 113     runner = unittest.TextTestRunner()
 114     runner.run(suite)