src/soc/simple/test/test_issuer_mmu.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 # test with MMU
  22 from openpower.test.mmu.mmu_cases import MMUTestCase
  23 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  24 #from openpower.test.ldst.ldst_cases import LDSTTestCase
  25 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  26
  27 if __name__ == "__main__":
  28     svp64 = True
  29     if len(sys.argv) == 2:
  30         if sys.argv[1] == 'nosvp64':
  31             svp64 = False
  32         sys.argv.pop()
  33
  34     print ("SVP64 test mode enabled", svp64)
  35
  36     unittest.main(exit=False)
  37     suite = unittest.TestSuite()
  38     #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64,
  39     #                          microwatt_mmu=True))
  40     #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
  41     #                          microwatt_mmu=True))
  42     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
  43                               microwatt_mmu=True))
  44     suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
  45                               microwatt_mmu=True,
  46                               rom=default_mem))
  47
  48     runner = unittest.TextTestRunner()
  49     runner.run(suite)